EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 91

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
© May 2009 Altera Corporation
Figure 4–9. Single-Port Memory
Note to
(1) You can implement two single-port memory blocks in a single M9K or M144K block. See
During a write operation, behavior of the RAM outputs is configurable. If you use the
read-enable signal and perform a write operation with the read enable deactivated,
the RAM outputs retain the values they held during the most recent active read
enable. If you activate read enable during a write operation, or if you are not using the
read-enable signal at all, the RAM outputs either show the new data being written,
the old data at that address, or a don’t care value. To choose the desired behavior, set
the read-during-write behavior to either new data, old data, or don’t care in the RAM
MegaWizard Plug-In Manager in the Quartus II software. See
on page 4–21
Table 4–4
in single-port mode.
Table 4–4. Stratix III Port Width Configurations for MLABs, M9K Blocks, and M144K Blocks
(Single-Port Mode)
Port Width
Configurations
Note to
(1) Configurations of 64 × 8, 64 × 9, 64 × 10, 32 × 16, 32 × 18, and 32 × 20 are supported by stitching multiple MLAB
page 4–5
blocks.
Figure
Port Width
Table
shows the possible port width configurations for TriMatrix memory blocks
for more details.
4–9:
4–4:
for more details on this behavior.
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
MLABs
16 × 10
16 × 16
16 × 18
16 × 20
inclock
16 × 8
16 × 9
(Note 1)
(1)
M9K Blocks
512 × 16
512 × 18
256 × 32
256 × 36
8 K × 1
4 K × 2
2 K × 4
1 K × 8
1 K × 9
outclock
q[]
Stratix III Device Handbook, Volume 1
“Read During Write”
“Packed Mode Support” on
M144K Blocks
16 K × 8
16 K × 9
8 K × 16
8 K × 18
4 K × 32
4 K × 36
2 K × 64
2 K × 72
4–11