EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 95

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
True Dual-Port Mode
Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode)
© May 2009 Altera Corporation
8K×1
4K×2
2K×4
1K×8
512×16
1K×9
512×18
Read Port
Stratix III M9K and M144K blocks support true dual-port mode. Sometimes called
bi-directional dual-port, this mode allows you to perform any combination of two
port operations: two reads, two writes, or one read and one write at two different
clock frequencies.
Figure 4–15. Stratix III True Dual-Port Memory
Note to
(1) True dual-port memory supports input/output clock mode in addition to the independent clock mode shown.
The widest bit configuration of the M9K and M144K blocks in true dual-port mode is
as follows:
■
■
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
configurations in true dual-port mode.
512 × 16-bit (×18-bit with parity) (M9K)
4K × 32-bit (×36-bit with parity) (M144K)
Figure
8K×1
4–15:
v
v
v
v
v
—
—
Figure 4–15
4K×2
v
v
v
v
v
—
—
Table 4–7
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
rden_a
aclr_a
q_a[]
clock_a
shows the true dual-port RAM configuration.
2K×4
v
v
v
v
v
—
—
lists the possible M9K block mixed-port width
(Note 1)
Write Port
1K×8
addressstall_b
v
v
v
v
v
—
—
address_b[]
byteena_b[]
data_b[ ]
clock_b
wren_b
rden_b
aclr_b
q_b[]
512×16
Stratix III Device Handbook, Volume 1
v
v
v
v
v
—
—
1K×9
v
v
—
—
—
—
—
512×18
—
—
—
—
—
v
v
4–15