XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 117

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Table 4-1: Dual-Port Names and Descriptions
Notes:
1. The
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
REGCE[A|B]
CASCADEIN[A|B]
CASCADEOUT[A|B]
“Data Parity Buses - DIP[A/B] and DOP[A/B]”
Port Name
(1)
(1)
www.xilinx.com
Figure 4-1: Dual-Port Data Flows
CASCADEOUTA
CASCADEINA
Data Input Bus
Data Input Parity Bus
Address Bus
Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state.
Set/Reset
Clock Input
Data Output Bus
Data Output Parity Bus
Output Register Enable
Cascade input pin for 32K x 1 mode
Cascade output pin for 32K x 1 mode
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
CLKA
CLKB
18-Kbit Block RAM
Synchronous Dual-Port and Single-Port RAMs
Memory
Port A
Port B
18 Kb
Array
CASCADEOUTB
section has more information on Data Parity pins.
CASCADEINB
DOPA
DOPB
DOA
DOB
Description
ug070_4_01_071204
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