XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet - Page 38

• Manufacturer Part Number: XC4VFX12-10FFG668C
• Description: IC FPGA VIRTEX-4 FX 12K 668FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10FFG668C

• Total Ram Bits: 663552
• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 668-BBGA, FCBGA
• No. Of Logic Blocks: 12312
• No. Of Macrocells: 12312
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1591; XC4VFX12-10FFG668C

Clock Buffers and Networks
Table 44: Global Clock Switching Characteristics (Including BUFGCTRL)
DCM and PMCD Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
Maximum Frequency
Outputs Clocks (Low Frequency Mode)
Input Clocks (Low Frequency Mode)
Outputs Clocks (High Frequency Mode)
T
T
T
F
CLKOUT_FREQ_1X_LF_MS_MIN
CLKOUT_FREQ_1X_LF_MS_MAX
CLKOUT_FREQ_2X_LF_MS_MIN
CLKOUT_FREQ_2X_LF_MS_MAX
CLKOUT_FREQ_DV_LF_MS_MIN
CLKOUT_FREQ_DV_LF_MS_MAX
CLKOUT_FREQ_FX_LF_MS_MIN
CLKOUT_FREQ_FX_LF_MS_MAX
CLKIN_FREQ_DLL_LF_MS_MIN
CLKIN_FREQ_DLL_LF_MS_MAX
CLKIN_FREQ_FX_LF_MS_MIN
CLKIN_FREQ_FX_LF_MS_MAX
PSCLK_FREQ_LF_MS_MIN
PSCLK_FREQ_LF_MS_MAX
CLKOUT_FREQ_1X_HF_MS_MIN
CLKOUT_FREQ_1X_HF_MS_MAX
CLKOUT_FREQ_2X_HF_MS_MIN
CLKOUT_FREQ_2X_HF_MS_MAX
CLKOUT_FREQ_DV_HF_MS_MIN
CLKOUT_FREQ_DV_HF_MS_MAX
T
do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only
needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
BCCCK_CE
BCCCK_S
BCCKO_O
MAX
BCCCK_CE
Symbol
/
T
/
and T
T
BCCKC_S
Symbol
BCCKC_CE
BCCKC_CE
(1)
(1)
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay
Global clock tree
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
Description
www.xilinx.com
Description
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(1,3,4,5,6)
(2,3,4)
0.27
0.00
0.27
0.00
0.70
500
-12
-12
150
300
100
210
150
210
500
150
500
300
500
333
9.4
32
64
32
32
2
1
1
Speed Grade
Speed Grade
0.31
0.00
0.31
0.00
0.77
-11
450
-11
150
300
100
210
150
210
450
150
450
300
450
300
9.4
32
64
32
32
2
1
1
0.35
0.00
0.35
0.00
0.90
-10
400
150
300
100
210
150
210
400
150
400
300
400
267
-10
9.4
32
64
32
32
2
1
1
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
ns
ns
ns
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