EP1C6Q240C6N Altera, EP1C6Q240C6N Datasheet - Page 50
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EP1C6Q240C6N
Manufacturer Part Number
EP1C6Q240C6N
Description
IC CYCLONE FPGA 5980 LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6Q240C6N
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
185
Frequency (max)
405.2MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1811
EP1C6Q240C6N
EP1C6Q240C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6Q240C6N
Manufacturer:
ALTERA
Quantity:
203
Part Number:
EP1C6Q240C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Cyclone Device Handbook, Volume 1
Figure 2–31. Control Signal Selection per IOE
2–44
Preliminary
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_csclr
io_caclr
io_cce_out
io_cce_in
io_cclk
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register is available for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, or the column and row interconnects.
Figure 2–32
shows the IOE in bidirectional configuration.
clk_in
clk_out
ce_in
ce_out
aclr/preset
Altera Corporation
sclr/preset
May 2008
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