EPF8452AQC160-4 Altera, EPF8452AQC160-4 Datasheet
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EPF8452AQC160-4
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EPF8452AQC160-4 Summary of contents
Page 1
... Table 1. FLEX 8000 Device Features Feature EPF8282A EPF8282AV Usable gates Flipflops Logic array blocks (LABs) Logic elements (LEs) Maximum user I/O pins Altera Corporation DS-F8000-11.1 ® Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see – 2,500 to 16,000 usable gates – 282 to 1,500 registers System-level features – ...
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... FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. General Altera’s Flexible Logic Element MatriX (FLEX benefits of both erasable programmable logic devices (EPLDs) and field- Description programmable gate arrays (FPGAs) ...
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... CMOS SRAM elements. FLEX 8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX 8000 devices via a serial data stream ...
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... FLEX 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. The FLEX 8000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL— ...
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... Block (LAB) IOE IOE Logic Element (LE) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns ...
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... LAB Control Signals 6 Dedicated Row Interconnect Inputs 4 4 Carry-In and Cascade-In from LAB on Left 4 2 LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 Figure 2 shows a block 8 See Figure 8 for details Column-to-Row Interconnect Column Interconnect Carry-Out and Cascade-Out to LAB on Right Altera Corporation ...
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... LABCTRL1 LABCTRL2 LABCTRL3 LABCTRL4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect ...
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... The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators. 8 shows how an n-bit full adder can be implemented LEs Altera Corporation ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX 8000 Carry Chain Operation Carry- Carry a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain Cascade Chain With the cascade chain, the FLEX 8000 architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel ...
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... Design performance can also be enhanced by designing for the operating mode that supports the desired application. 10 shows how the cascade function can connect adjacent LEs to OR Cascade Chain LE1 d[3..0] LE2 d[7.. d[(4 n- 1)..4( n- 1)] LE1 LUT LE2 LUT LE n LUT Altera Corporation ...
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... Clearable Counter Mode Carry-In (ena) data1 (nclr) data2 data3 (data) (nload) data4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Cascade-In 4-Input LUT Cascade-Out Cascade-In 3-Input LUT Cascade-Out 3-Input LUT Carry-Out Cascade-In 3-Input 1 ...
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... Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a synchronous clear. 12 Altera Corporation ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. ...
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... NOT Asynchronous Load without Clear or Preset NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT 14 Asynchronous Preset LABCTRL1 or LABCTRL2 PRN D Q CLRN PRN Q D CLRN PRN Q D CLRN PRN Q D CLRN Asynchronous Clear & Preset LABCTRL1 PRN D Q CLRN LABCTRL2 Altera Corporation ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl asynchronously loads a 1 into the register ...
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... Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect 16 shows how an LE drives the row and column interconnect. Row Channels (1) Each LE drives one row channel. LE1 LE2 Note: (1) See Table 4 for the number of row channels. to Local to Local Each LE drives up to Feedback Feedback two column channels. Altera Corporation 16 Column Channels ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB can drive up to two separate column interconnect channels. Therefore, all 16 available column channels can be driven by the LAB. The column channels run vertically across the entire device, and share access to LABs in the same column but in different rows. The MAX+PLUS II Compiler chooses which LEs must be connected to a column channel ...
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... IOE IOE IOE Row Interconnect LAB A2 LAB B2 Cascade & Carry Chain IOE IOE IOE Figure 10 shows the IOE block diagram. See Figure 12 for details. See Figure 11 for details. IOE 1 IOE 8 IOE 1 IOE 8 Altera Corporation ...
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... Figure 10. FLEX 8000 IOE Numbers in parentheses are for EPF81500A devices only. To Row or Column Interconnect From Row or Column Interconnect Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet I/O Controls 6 Programmable (6) Inversion VCC VCC Row-to-IOE Connections Figure 11 illustrates the connection between row interconnect channels and IOEs ...
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... Figure separate column channels. The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. 20 Note (1 168 (216 12). When an IOE is used as an input, it can drive up to two IOE 1 IOE 2 IOE 3 IOE 4 IOE 5 IOE 6 IOE 7 IOE Altera Corporation ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX 8000 Column-to-IOE Connections Each IOE is driven by an IOE 8-to-1 multiplexer. 8 Column Interconnect In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated input pins. These dedicated inputs provide low-skew, device- wide signal distribution, and are typically used for global clock, clear, and preset control signals ...
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... The number of row channels in a row that can drive the Numbers in parentheses are for EPF81500A devices. 4 Dedicated Inputs 1 2 Row Channels ( for EPF8282A and EPF8282AV devices for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices for EPF81500A devices. Peripheral Control Signals Programmable Inversion Altera Corporation ...
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... OE6 – OE7 – OE8 – OE9 Output Configuration f Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 5 lists the source of the peripheral control signal for each FLEX 8000 device by row. EPF8452A EPF8636A Row A Row A Row B Row C Row A ...
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... CC level, input voltages are at TTL levels and are therefore CCINT 26. Description levels lower than 4.75 V CCIO instead See Table 8 OD2 OD1 Table 6. Altera Corporation ...
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... FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms Table 8 EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 7. FLEX 8000 Boundary-Scan Register Length Device EPF8282A, EPF8282AV EPF8636A ...
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... For detailed information on JTAG operation in FLEX 8000 devices, refer to Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Each FLEX 8000 device is functionally tested and specified by Altera. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for ...
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... Storage temperature STG T Ambient temperature AMB T Junction temperature J Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-ground- ...
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... V + 0.5 CCINT 0 V CCIO 0 70 – (5), (6) Min Typ Max 2 0.5 CCINT –0.5 0.8 2.4 2.4 V – 0.2 CCIO 0.45 0.45 0.2 –10 10 –40 40 0.5 10 Altera Corporation Unit ° C ° Unit µA µA mA ...
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... C Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) The maximum V rise time is 100 ms. ...
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... C Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage is –0.3 V. During transitions, the inputs may undershoot to –2 overshoot to 5.3 V for input currents less than 100 mA and periods shorter than 20 ns. (3) The maximum V rise time is 100 ms. V ...
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... Output Voltage (V) Figure 17 EPF8282A devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V Figure 18 devices. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet I OL Typical I Output Current (mA ...
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... The Timing Analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. Tables 17 through 20 describe the FLEX 8000 timing parameters and their symbols 3 Room Temperature Output Voltage (V) Altera Corporation 4 ...
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... LE register setup time before clock; LE register recovery time after asynchronous preset, clear load t LE register hold time after clock register preset delay PRE t LE register clear delay CLR Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Note (1) Parameter = 5 CCIO = 3 CCIO ( CCIO = 3 ...
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... ODH Notes to tables: (1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and external parameters specified by Altera. Internal timing parameters should be used for estimating device performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. (2) These values are specified in ...
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ROW Carry-In from Cascade-In from Previous LE Previous LE Cascade Gate Delay LUT Delay t LUT t t RLUT GATE t CLUT Carry Chain Delay t t LOCAL CGEN t CGENR t CICO Register Control CASC ...
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... COL ROW A-4 Max Min Max 0.8 0.9 1.8 1.9 1.8 1.9 1.0 1.0 0.2 0.1 1.8 0.0 1.2 1.2 1.6 1.7 1.4 1.7 – – 4.9 5.2 1.6 1.8 1.6 1.8 – – 5.1 5.3 Altera Corporation + t LOCAL + t LOCAL Unit ...
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... Table 23. EPF8282A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 4.2 2.5 5.0 7.2 5.0 A-4 Max Min Max ...
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... A-4 Max Min Max 19.8 24.8 1.0 Altera Corporation Unit Unit ns ns ...
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... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 26. EPF8282AV I/O Element Timing Parameters Symbol A-3 Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.8 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 27. EPF8282AV Interconnect Timing Parameters Symbol ...
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... Speed Grade A-4 Max Min Max 24.8 50.1 1.0 Unit Unit ns ns Altera Corporation ...
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... Table 31. EPF8452A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 – 4.6 1 ...
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... A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...
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... Table 35. EPF8636A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1 ...
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... A-4 Max Min 2.3 0.2 1.6 0.0 0.7 0.5 0.9 1.4 1.8 4.0 4.0 0.5 0.5 1.1 1.4 0.7 0.7 A-3 A-4 Max Min 20.0 1.0 Altera Corporation Unit Max 3.0 ns 0.1 ns 1.6 ns 0.0 ns 0.9 ns 0.6 ns 0.8 ns 1 0.6 ns 0.6 ...
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... Table 39. EPF8820A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1 ...
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... A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...
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... Table 43. EPF81188A Interconnect Timing Parameters Symbol t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 Min Max Min 0.7 1.7 1.7 1.0 0.3 1.4 1.6 0.0 0.0 1.2 1.5 1 ...
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... A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...
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... Table 47. EPF81500A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1 ...
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... A-4 Max Min Max 20.1 25.1 1.0 Altera Corporation Unit Unit ns ns ...
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... Figure 20 for several LE utilization values. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet + P = [(I INT IO CCSTANDBY values are shown as I CCSTANDBY IO Application Note 74 (Evaluating Power for Altera value depends on the switching frequency and CCACTIVE : CCACTIVE MAX AC TIVE ...
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... For more information Devices) and Application Note 38 (Configuring Multiple FLEX 8000 vs. Operating Frequency 30 Frequency (MHz) 30 Frequency (MHz) Application Note 33 (Configuring FLEX 8000 Altera Corporation 1,500 LEs 1,000 LEs 500 LEs 60 200 LEs 150 LEs 100 LEs 50 LEs 60 Devices). ...
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... Configuration Scheme Active serial Active parallel up Active parallel down Passive serial Passive parallel synchronous Passive parallel asynchronous Table 51 Acronym Data Source AS Altera configuration device APU Parallel configuration device APD Parallel configuration device PS Serial data path PPS Intelligent host PPA Intelligent host ...
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... TQFP PGA EPF8452A EPF8820A EPF8452A 76 110 R1 75 109 C13 26 38 A15 100 143 P14 1 144 N13 23 33 F13 D15 21 3 E15 102 K2 71 103 K1 72 104 K3 73 105 M1 160-Pin PQFP EPF8820A ( 125 124 87 89 110 118 121 100 107 Altera Corporation ...
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... DATA0 (3) 79 SDOUT (4) 55 TDI (4) 27 TDO TCK (4), (6) 72 (4) 20 TMS (7) 52 TRST Dedicated 12, 31, 54, Inputs (10) 73 17, 38, 59, VCCINT 80 – VCCIO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 84-Pin 100-Pin 100-Pin PLCC TQFP EPF8452A EPF8282A EPF8452A EPF8636A EPF8282AV ...
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... TQFP PGA EPF8820A EPF8452A 7, 17, 27, C12, D4, 39, 54, D7, D9, 80, 81, D13, G4, 100,101, G13, H3, 128, 142 H12, J4, J13, L1, M3, M8, M12, M15, N4 – – 108 116 Altera Corporation 160-Pin PQFP EPF8820A (1) 12, 13, 34, 35, 51, 63, 75, 80, 83, 93, 103, 115, 126, 131, 143, 155 – 116 ...
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... ADD6 104 ADD5 105 ADD4 106 ADD3 109 ADD2 110 ADD1 123 ADD0 144 DATA7 150 DATA6 152 DATA5 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 160-Pin 192-Pin PGA PQFP EPF8636A EPF8636A EPF8820A 1 R15 3 T15 120 C15 ...
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... Altera Corporation 208-Pin PQFP EPF81188A (1) 170 168 166 163 161 119 – ...
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... G11 ADD6 F14 ADD5 E13 ADD4 D15 ADD3 D14 ADD2 E12 ADD1 C15 ADD0 A7 DATA7 D7 DATA6 A6 DATA5 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A C14 237 G15 21 L15 40 L3 141 R4 117 C4 184 ...
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... E14, R7, R9, 236 R11, R13, R14, T14 17, 39, 61, 78, D14, E7, E9, 94, 108, 130, E11, E13, R6, 152, 174, 191, R8, R10, R12, 205, 221, 235 T13, T15 Altera Corporation 304-Pin RQFP EPF81500A 248 246 243 241 239 169 80 (14) 149 ...
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... H9, H10, H11, J6, J7, J8, J9, J10, K6, K7, K8, K9, K11, L15, N3 Connect – (N.C.) Total User I/O 148 Pins (9) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A A1, D6, E11 30, 31, E7, E9, G4, 52, 53, 72, 90, G5, G13, ...
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... FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) Perform a complete thermal analysis before committing a design to this device package. See (Evaluating Power for Altera Devices) (2) This pin is a dedicated pin and is not available as a user I/O pin. (3) SDOUT will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the MAX+PLUS II software will not use SDOUT as a user I/O pin ...