EPF10K10TI144-4N Altera, EPF10K10TI144-4N Datasheet - Page 14
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EPF10K10TI144-4N
Manufacturer Part Number
EPF10K10TI144-4N
Description
IC FLEX 10K FPGA 10K 144-TQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K10TI144-4N
Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
6144
Number Of I /o
102
Number Of Gates
31000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K10TI144-4N
Manufacturer:
Altera
Quantity:
135
Part Number:
EPF10K10TI144-4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 6. FLEX 10K Logic Element
14
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Chip-Wide
labctrl1
labctrl2
labctrl3
labctrl4
Reset
data1
data2
data3
data4
Look-Up
Preset
Clear/
Logic
Select
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks;
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LEs
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous enable, a carry chain, and a
cascade chain. Each LE drives both the local and the FastTrack
Interconnect. See
Clock
(LUT)
Table
Carry-Out
Carry-In
Chain
Carry
Cascade-Out
Cascade-In
Figure
Cascade
Chain
6.
Register Bypass
D
ENA
CLRN
PRN
Q
Programmable
Register
Altera Corporation
To FastTrack
Interconnect
To LAB Local
Interconnect