EPF10K50RI240-4 Altera, EPF10K50RI240-4 Datasheet - Page 31

• Manufacturer Part Number: EPF10K50RI240-4
• Description: IC FLEX 10K FPGA 50K 240-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K50RI240-4

• Number Of Logic Elements/cells: 2880
• Number Of Labs/clbs: 360
• Total Ram Bits: 20480
• Number Of I /o: 189
• Number Of Gates: 116000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2240

Altera Corporation
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices; it provides up to 12 peripheral control signals that
can be allocated as follows:
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, an LE in a different row can drive a column interconnect,
which causes a row interconnect to drive the peripheral control signal.
The chip-wide reset signal will reset all IOE registers, overriding any other
control signals.
Tables 8
rows that can drive global signals. These tables also show how the output
enable, clock enable, clock, and clear signals share 12 peripheral control
signals.
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
and
9
list the sources for each peripheral control signal, and the
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