EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 135
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
Notes to
(1)
(2)
Power-On Reset
Circuitry
Altera Corporation
May 2007
This is the logic array signal or the larger of either the V
This is the larger of either the V
Figure
4–2:
n+
Logic Array
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the V
levels and tri-states all the user I/O pins while V
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank V
V
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the V
condition during user mode can be detected. If there is a V
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
When power is applied to a Stratix II device, a power-on-reset event
occurs if V
period of time (specified as a maximum V
V
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSEL pin is connected to ground, the POR
time is 100 ms. When the PORSEL pin is connected to V
is 12 ms.
p-well
Signal
CCINT
CC
CCIO
rise time for Stratix II device is 100 ms. Stratix II devices provide a
voltage, reach an acceptable level before configuration is
or V
n+
CC
PAD
reaches the recommended operating range within a certain
signal.
V
CCIO
PAD
voltages, V
CCIO
p+
CCINT
or V
PAD
(1)
voltage level so that a brown-out
CCPD
signal.
Stratix II Device Handbook, Volume 1
n-well
voltage, as well as the logic array
V
CCIO
p+
Hot Socketing & Power-On Reset
CCINT
CC
rise time). The maximum
, V
(2)
n+
CC
CCIO
p-substrate
is ramping up until
, and V
CC
, the POR time
CCINT
CCPD
voltage
voltage
4–5