EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 147
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Note to
(1)
V
V
V
V
V
V
V
V
V
V
V
(DC)
V
V
(AC)
V
ΔV
V
(AC)
Symbol
Symbol
Table 5–17. SSTL-18 Class II Specifications
Table 5–18. SSTL-18 Class I & II Differential Specifications
CCIO
REF
TT
IH
IL
IH
IL
OH
OL
CCIO
SWING
X
SWING
ISO
OX
ISO
(AC) AC differential input cross
(DC) Low-level DC input voltage
(AC) Low-level AC input voltage
(DC) High-level DC input voltage
(AC) High-level AC input voltage
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table
Output supply voltage
DC differential input voltage
point voltage
AC differential input voltage
Input clock signal offset
voltage
Input clock signal offset
voltage variation
AC differential cross point
voltage
Output supply voltage
Reference voltage
Termination voltage
High-level output voltage
Low-level output voltage
5–17:
Parameter
Parameter
Conditions
I
I
OH
OL
= 13.4 mA
= –13.4 mA
Conditions
(V
(V
(1)
CCIO
CCIO
(1)
Minimum
/2) – 0.175
/2) – 0.125
1.71
0.25
0.5
V
V
V
V
Minimum
REF
CCIO
REF
REF
0.855
1.71
+ 0.125
– 0.04
+ 0.25
– 0.28
Stratix II Device Handbook, Volume 1
0.5 × V
Typical
±200
1.80
DC & Switching Characteristics
CCIO
Typical
0.900
V
1.80
REF
(V
(V
CCIO
CCIO
Maximum
V
V
V
Maximum
/2) + 0.175
/2) + 0.125
REF
1.89
REF
REF
0.945
1.89
0.28
– 0.125
+ 0.04
– 0.25
5–11
Unit
Unit
mV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V