EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 54
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
2–46
Stratix II Device Handbook, Volume 1
C4 Interconnect
LAB
18
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
16
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
Row Interface
36
12
Block
36 Inputs per Row
R4 Interconnect
16
Control
A[17..0]
B[17..0]
DSP Block
Row Structure
OA[17..0]
OB[17..0]
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
36
Altera Corporation
Direct Link Interconnect
from Adjacent LAB
May 2007
LAB