EP2S30F672C5N Altera, EP2S30F672C5N Datasheet - Page 56
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EP2S30F672C5N
Manufacturer Part Number
EP2S30F672C5N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
500
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Family Type
Stratix II
No. Of I/o's
500
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1898
EP2S30F672C5N
EP2S30F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
PLLs & Clock Networks
PLLs & Clock
Networks
2–48
Stratix II Device Handbook, Volume 1
Stratix II devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix II devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to
24 clocks per device region with low skew and delay. This hierarchical
clocking scheme provides up to 48 unique clock domains in Stratix II
devices.
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in
PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the
selection of the clock source and dynamically enables/disables the clock
to reduce power consumption.
features.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
Note to
(1)
Number per device
Number available per
quadrant
Sources
Dynamic clock source
selection
Dynamic enable/disable
Table 2–8. Global & Regional Clock Features
Dynamic source clock selection is supported for selecting between CLKp pins and
PLL outputs only.
Table
Feature
Figures 2–31
2–8:
and 2–32. Internal logic and enhanced and fast
CLK pins, PLL outputs,
or internal logic
Table 2–8
Global Clocks
v
v
16
16
(1)
shows global and regional clock
CLK pins, PLL outputs,
or internal logic
Regional Clocks
Altera Corporation
v
32
8
May 2007