EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 45
EP2SGX30CF780C4N
Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N
EP2SGX30CF780C4N
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Altera Corporation
October 2007
The receiver PLL can also drive the regional clocks and regional routing
adjacent to the associated transceiver block.
global clock resource can be used by the recovered clock.
shows which regional clock resource can be used by the recovered clock.
Figure 2–30. Stratix II GX Receiver PLL Recovered Clock to Global Clock
Connection
Notes to
(1)
(2)
CLK[3..0]
CLK# pins are clock pins and their associated number. These are pins for global
and regional clocks.
GCLK# pins are global clock pins.
Figure
7
1
2
8
2–30:
Notes
GCLK[3..0]
(1),
(2)
GCLK[15..12]
CLK[15..12]
GCLK[4..7]
CLK[7..4]
Stratix II GX Device Handbook, Volume 1
11 5
12 6
Figure 2–30
GCLK[11..8]
Stratix II GX Architecture
shows which
Figure 2–31
Stratix II GX
Stratix II GX
Transceiver
Transceiver
Block
Block
2–37
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