EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 116

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

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IEEE Std. 1149.1 JTAG Boundary-Scan Support
3–2
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
SignalTap II
instructions
Table 3–1. Stratix II JTAG Instructions
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for
Altera Devices White Paper.
(1)
(1)
(1)
Table
(2)
3–1:
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
Instruction Code
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit
TDI
out of
Selects the
allowing the
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Stratix II device via the JTAG port with a
USB Blaster, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II
download cable, or when using a .jam or .jbc via an embedded
processor or JRunner.
Emulates pulsing the
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during configuration.
Once issued, the
reset the configuration device.
configuration register is loaded and the TAP controller state
machine transitions to the
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
and
TDO
TDO
.
IDCODE
IDCODE
pins, allowing the
CONFIG_IO
USERCODE
register and places it between
nCONFIG
to be serially shifted out of
UPDATE_DR
Description
register and places it between the
nSTATUS
instruction holds
pin low to trigger reconfiguration
USERCODE
state.
is held low until the IOE
TDI
TDI
TDI
to be serially shifted
Altera Corporation
nSTATUS
TDO
and
and
and
TDI
.
TDO
TDO
TDO
and
May 2007
low to
pins,
pins,
pins,
TDO
,

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