EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 69

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
450
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
531
Altera Corporation
May 2007
Figure 2–41. Global & Regional Clock Connections from Center Clock Pins &
Fast PLL Outputs
Notes to
(1)
(2)
EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the
connectivity from these four PLLs to the global and regional clock networks
remains the same as shown.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Figure
2–41:
Note (1)
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–61

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