XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 115

• Manufacturer Part Number: XC3S250E-4FTG256C
• Description: IC SPARTAN-3E FPGA 250K 256-FTBG
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FTG256C

• Total Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• No. Of Logic Blocks: 5508
• No. Of Gates: 250000
• No. Of Macrocells: 5508
• No. Of Speed Grades: 4
• No. Of I/o's: 190
• Clock Management: DLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1482

Revision History
The following table shows the revision history for this document.
DS312-2 (v3.8) August 26, 2009
Product Specification
03/01/05
03/21/05
11/23/05
03/22/06
04/10/06
05/19/06
Date
R
Version
1.0
1.1
2.0
3.0
3.1
3.2
Initial Xilinx release.
Updated
Updated values of
configuration bitstream sizes for XC3S250E through XC3S1600E in
Table
Added
Configuration. Added Stepping 0 limitations when
mode. Added
Managers (DCMs)
enhanced the clock infrastructure diagram in
Considerations
VS[2:0] Pins
in
‘D’-series DataFlash. Updated the
Added
Families, and
sections to BPI configuration mode topic. Updated and amplified
FPGAs
Upgraded data sheet status to Preliminary. Updated
Added clarification that Input-only pins also have
Added design note about address setup and hold requirements to
warning message about software differences between ISE 8.1i, Service Pack 3 and earlier
software to
about using GCLK1 in
Figure
Configuration. Highlighted which pins have configuration pull-up resistors unaffected by
HSWAP in
in
PROMs can be used in Commercial temperature range applications in
Figure
Images Using MultiBoot Option
software support to BPI
Added
production stepping differences in
Updated
shows electrical connectivity and corrected left- and right-edge DCM coordinates. Updated
Table
BUFGMUX primitive. Corrected the coordinate locations for the associated BUFGMUX
primitives in
preferred connection to a BUFGMUX.
Made further clarifying changes to
primitives and to DCMs. Added Atmel AT45DBxxxD-series DataFlash serial PROMs to
Table
daisy-chain must be from either the Spartan-3E or the Virtex-5 FPGA families (see BPI
Daisy-Chaining). Added
Design. Minor updates to
product options support the Readback feature, shown in
Table 53
Table
57, and
30,
53. Added details that intermediate FPGAs in a BPI-mode, multi-FPGA configuration
Power-On Precautions if PROM Supply is Last in
45. Added additional information on HSWAP behavior to
54. Updated
No Internal Charge Pumps or Free-Running
Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI
section. Added
45,
Figure
JTAG User ID
Table
Table
FIXED Phase Shift Mode
and
Table
Table 31
section. Added Spansion, Winbond, and Macronix to list of SPI Flash vendors
Table
Multiplier/Block RAM Interaction
BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs
31, and
Table
45. Modified title on
section. Added
46. Updated bitstream image sizes for the XC3S1200E and XC3S1600E
51,
On-Chip Differential Termination
section, especially
Figure
60. Added
and
Table
56. Clarified that SPI mode configuration supports Atmel ‘C’- and
www.xilinx.com
DLL Clock Input Connections
Daisy-Chaining
Production Stepping
Table 32
information. Clarified Note 1,
Using JTAG Interface to Communicate to a Configured FPGA
Table
Figure 67
56. Updated
57, and
DLL Performance Differences Between
32. Updated
Design Considerations for the HSWAP, M[2:0], and
to show the specific clock line driven by the associated
section. Added design note about BPI daisy-chaining
Table
Programming Support
Figure
Table
Table 39
and
and
Phase Shifter (PS)
Dynamically Loading Multiple Configuration
Revision
section. Updated JTAG revision codes in
71. Updated
Figure
60. Clarified that ‘B’-series Atmel DataFlash SPI
VARIABLE Phase Shift
46, showing both direct inputs to BUFGMUX
Figure 45
Table 41
and
section.
68. Clarified which Spartan-3E FPGA
Pull-Up and Pull-Down
section. Updated
Table
Daisy-Chaining
Input Delay Functions
Software Version
Figure
Oscillators. Updated information on
resistors. Updated
to show that the I0-input is the
and
and
45.
Table
Table
portion. Corrected and
Sequence,
section for SPI Flash PROMs.
Clock
5. Clarified that
68.
Pin Behavior During
41. Added
Powering Spartan-3E
Inputs. Updated
Block
Mode. Added message
Functional Description
Digital Clock
Table
in SPI configuration
Table 53
Compatible Flash
Requirements.
Table
RAM. Added
Steppings.
45,
Resistors.
CCLK Design
and
Figure 45
Table
7. Updated
and
Table
Figure
51,
67.
6.
115