EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 222
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–62
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
Cyclone III Device Handbook, Volume 1
FACTORY
ACTIVE_DISENGAGE
CONFIG_IO
JTAG Boundary Scan Instructions (no
JTAG_PROGRAM)
JTAG Instruction
I/O Reconfiguration
Use the CONFIG_IO instruction to reconfigure the I/O configuration shift register
(IOCSR) chain. This instruction allows you to perform board-level testing prior to
configuring the Cyclone III device family or waiting for a configuration device to
complete configuration. After the configuration is interrupted and JTAG testing is
complete, the part must be reconfigured using the PULSE_NCONFIG JTAG
instruction or by pulsing the nCONFIG pin low.
You can issue the CONFIG_IO instruction any time during user mode. The
CONFIG_IO instruction cannot be issued when nCONFIG pin is asserted low (during
power up) or immediately after issuing a JTAG instruction that triggers
reconfiguration. For more information about the wait-time for issuing the CONFIG_IO
instruction, refer to
When using CONFIG_IO instruction, you must meet the following timing restrictions:
■
■
■
Table 9–18. Wait Time for Issuing the CONFIG_IO Instruction
Use the ACTIVE_DISENGAGE instruction with CONFIG_IO instruction to interrupt
configuration.
CONFIG_IO usage scenarios.
Wait time after the nCONFIG pin is released
Wait time after PULSE_NCONFIG or ACTIVE_ENGAGE is
issued
CONFIG_IO instruction cannot be issued during the nCONFIG pin low
Observe 230 μs minimum wait time after any of the following conditions are met:
■
■
■
Wait 230 μs after power up with nCONFIG pin high before issuing the CONFIG_IO
instruction (or wait for the nSTATUS pin to go high)
nCONFIG pin goes high
Issuing the PULSE_NCONFIG instruction
Issuing the ACTIVE_ENGAGE instruction, before issuing the CONFIG_IO
instruction
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–19
NA
PS
O
R
O
Table
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
Wait Time
Configuration)
(Interrupting
FPP
NA
O
R
O
9–18.
lists the sequence of instructions to use for various
NA
AS
O
R
O
AP
(4)
NA
O
R
O
PS
NA
O
R
O
(Note 1)
User Mode
FPP
NA
O
R
O
(Part 1 of 2)
NA
AS
© December 2009 Altera Corporation
O
R
O
NA
AP
(4)
O
O
R
230 ms
230 ms
Time
NA
PS
—
—
Configuration Features
R
Power Up
FPP AS
NA
—
—
R
—
NA NA
—
R
AP
(4)
NA
—
—