EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 256
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
11–2
Configuration Error Detection
User Mode Error Detection
Cyclone III Device Handbook, Volume 1
1
In configuration mode, a frame-based CRC is stored in the configuration data and
contains the CRC value for each data frame.
During configuration, Cyclone III device family calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or all the
values are calculated.
For Cyclone III device family, the CRC is computed by the Quartus
downloaded into the device as part of the configuration bit stream. These devices
store the CRC in the 32-bit storage register at the end of the configuration mode.
Soft errors are changes in a configuration random-access memory (CRAM) bit state
due to an ionizing particle. Cyclone III device family has built-in error detection
circuitry to detect data corruption by soft errors in the CRAM cells.
This error detection capability continuously computes the CRC of the configured
CRAM bits based on the contents of the device and compares it with the
pre-calculated CRC value obtained at the end of the configuration. If the CRCs match,
there is no error in the current configuration CRAM bits. The process of error
detection continues until the device is reset (by setting nCONFIG to low).
The Cyclone III device family error detection feature does not check memory blocks
and I/O buffers. These device memory blocks support parity bits that are used to
check the contents of memory blocks for any error. The I/O buffers are not verified
during error detection because the configuration data uses flip-flops as storage
elements that are more resistant to soft errors. Similar flip-flops are used to store the
pre-calculated CRC and other error detection circuitry option bits.
The error detection circuitry in Cyclone III device family uses a 32-bit CRC IEEE 802
standard and a 32-bit polynomial as the CRC generator. Therefore, a single 32-bit CRC
calculation is performed by the device. If a soft error does not occur, the resulting
32-bit signature value is 0x000000, which results in a 0 on the output signal
CRC_ERROR. If a soft error occurs in the device, the resulting signature value is
non-zero and the CRC_ERROR output signal is 1.
You can inject a soft error by changing the 32-bit CRC storage register in the CRC
circuitry. After verifying the failure induced, you can restore the 32-bit CRC value to
the correct CRC value using the same instruction and inserting the correct value.
Be sure to read out the correct value before updating it with a known bad value.
In user mode, Cyclone III device family supports the CHANGE_EDREG JTAG
instruction, which allows you to write to the 32-bit storage register. You can use Jam
STAPL files (.jam) to automate the testing and verification process. This instruction
can only be executed when the device is in user mode, and it is a powerful design
feature that enables you to dynamically verify the CRC functionality in-system
without having to reconfigure the device. You can then switch to use the CRC circuit
to check for real errors induced by an SEU.
Chapter 11: SEU Mitigation in the Cyclone III Device Family
© December 2009 Altera Corporation
Configuration Error Detection
®
II software and
™