EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 74
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
5–10
Cyclone III Device Family PLL Hardware Overview
Figure 5–6. Cyclone III Device Family PLL Block Diagram
Notes to
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
External Clock Outputs
Cyclone III Device Handbook, Volume 1
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
pfdena
Clock inputs
Figure
GCLK
from pins
(3)
5–6:
1
4
This section gives a hardware overview of the Cyclone III device family PLL.
Figure 5–6
the Cyclone III device family.
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f
Cyclone III LS Device Data Sheet
Each PLL of the Cyclone III device family supports one single-ended clock output or
one differential clock output. Only the C0 output counter can feed the dedicated
external clock outputs, as shown in
Other output counters can feed other I/O pins through the GCLK.
inclk0
inclk1
Switchover
Clock
Block
shows a simplified block diagram of the major components of the PLL of
VCO
÷n
clkswitch
clkbad0
clkbad1
activeclock
specification specified in the
PFD
LOCK
circuit
chapters.
(Note 1)
CP
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
lock
Detector
Figure
Range
VCO
LF
VCO
5–7, without going through the GCLK.
8
VCOOVRR
VCOUNDR
no compensation;
source-synchronous;
normal mode
Cyclone III Device Data Sheet
÷2 (2)
ZDB mode
Cyclone III Device Family PLL Hardware Overview
8
© December 2009 Altera Corporation
÷M
÷C0
÷C2
÷C4
÷C1
÷C3
output
PLL
mux
GCLKs
External clock
output
GCLK
networks
and