EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 206
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–46
Cyclone III Device Handbook, Volume 1
f
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave nCEO pins floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals can require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered. Devices must be of the same density and package. All devices start and
complete configuration at the same time.
Figure 9–22
family is receiving the same configuration data.
Figure 9–22. Multi-Device FPP Configuration Using an External Host When Both Devices Receive the
Same Data
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
You can use a single configuration chain to configure Cyclone III device family with
other Altera devices that support the FPP configuration. To ensure that all devices in
the chain complete configuration at the same time or that an error flagged by one
device starts reconfiguration in all devices, tie all the device CONF_DONE and
nSTATUS pins together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
chain. V
configuration data into multiple devices.
refer to
overshoot equation outlined in
(MAX II Device or
Microprocessor)
External Host
Figure
ADDR
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–7 on page
CC
Memory
must be high enough to meet the V
shows multi-device FPP configuration when both Cyclone III device
DATA[7..0]
9–22:
10 k
V CCIO (1) V CCIO (1)
9–11. Connect the MSEL pins directly to V
“Configuration and JTAG Pin I/O Requirements” on page
10 k
GND
Configuring Mixed Altera FPGA Chains
Buffers (4)
Cyclone III Device Family 1
IH
specification of the I/O on the device and the external host.
CONF_DONE
nSTATUS
nCE
DATA[7..0] (4)
nCONFIG
DCLK (4)
MSEL[3..0]
nCEO
(3)
N.C. (2)
CCA
or GND.
© December 2009 Altera Corporation
GND
Cyclone III Device Family 2
CONF_DONE
nSTATUS
nCE
DATA[7..0] (4)
nCONFIG
DCLK (4)
9–7.
MSEL[3..0]
Configuration Features
chapter in
nCEO
N.C. (2)
(3)