EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 224
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–64
Table 9–20. JTAG Programming Instruction Flows
Cyclone III Device Handbook, Volume 1
FACTORY
ACTIVE_DISENGAGE
CONFIG_IO
Other JTAG instructions
JTAG_PROGRAM
CHECK_STATUS
JTAG_STARTUP
JTAG TAP Reset/ other instruction
Notes to
(1) “R” indicates that the instruction is required to be executed before the next instruction, “O” indicates the optional instruction, “Rc” indicates
(2) AP configuration is for Cyclone III devices only.
the recommended instruction, and “NA” indicates that the instruction is not allowed to be executed in this mode.
Table
JTAG Instruction
9–20:
ACTIVE_DISENGAGE
The ACTIVE_DISENGAGE instruction places the active configuration controller (AS
and AP) into an idle state prior to JTAG programming. The active configuration
controller is the AS controller when the MSEL pins are set to AS configuration scheme
and the AP controller when the MSEL pins are set to the AP configuration scheme.
The two purposes of placing the active controllers in an idle state are:
■
■
The ACTIVE_DISENGAGE instruction is required before JTAG programming
regardless of the current state of the Cyclone III device family if the MSEL pins are set
to an active configuration scheme (AS or AP). If the ACTIVE_DISENGAGE instruction
is issued during a passive configuration scheme (PS or FPP), it has no effect on the
Cyclone III device family. Similarly, the CONFIG_IO instruction is issued after an
ACTIVE_DISENGAGE instruction, but is no longer required to properly halt
configuration.
for each configuration mode. The ordering of the required instructions is a hard
requirement and must be met to ensure functionality.
In AS or AP configuration schemes, the ACTIVE_DISENGAGE instruction puts the
active configuration controllers into idle state. If a successful JTAG programming is
executed, the active controllers are automatically re-engaged after user mode is
reached using JTAG programming. This causes the active controllers to transition to
their respective user mode states.
To ensure that they are not trying to configure the device in their respective
configuration modes during JTAG programming
To allow the controllers to properly recognize a successful JTAG programming
that results in the device reaching user mode
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–20
NA
PS
Rc
Rc
O
O
R
R
R
Prior to User Mode
Configuration Scheme and Current State of the Cyclone III Device
Configuration)
(Interrupting
FPP
(Note 1)
NA
Rc
Rc
lists the required, recommended, and optional instructions
O
O
R
R
R
NA
AS
Rc
R
O
O
R
R
R
(2)
NA
AP
Rc
R
O
O
R
R
R
NA
PS
Rc
O
O
O
R
R
R
User Mode
FPP
NA
Rc
O
O
O
R
R
R
NA
AS
Rc
O
O
O
R
R
R
© December 2009 Altera Corporation
(2)
NA
AP
Rc
R
O
O
R
R
R
NA
PS
Rc
R
O
O
R
R
R
Configuration Features
FPP
Power Up
NA
Rc
R
O
O
R
R
R
NA
AS
Rc
R
R
O
R
R
R
AP(
NA
NA
Rc
2)
R
O
R
R
R