EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 227
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Device Configuration Pins
Table 9–21. Cyclone III Device Family Configuration Pin Summary (Part 1 of 2)
© December 2009
Bank
1
6
1
1
8
8
6
1
1
1
6
1
1
1
1
6
6
6
1
7
8
6
1
6
6
6
FLASH_nCE, nCSO
CRC_ERROR
DATA[0]
DATA[1], ASDO
DATA[7..2]
DATA[15..8]
INIT_DONE
nSTATUS
nCE
DCLK
CONF_DONE
TDI
TMS
TCK
nCONFIG
CLKUSR
nCEO
MSEL[3..0]
TDO
PADD[14..0]
PADD[19..15]
PADD[23..20]
nRESET
nAVD
nOE
nWE
1
Description
Altera Corporation
The APFC_BOOT_ADDR instruction is retained after reconfiguration while the system
board is still powered on. However, you must reprogram the instruction whenever
you restart the system board.
Table 9–21
configuration-related pins on Cyclone III device family.
Table 9–21
through
lists the Cyclone III device family pin configuration.
Input/Output
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table 9–23
Dedicated
describe the connections and functionality of all the
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
CC IO
Powered By
/Pull-up
Pull-up
Pull-up
Pull-up
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C CINT
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
CC IO
(1)
Cyclone III Device Handbook, Volume 1
Configuration Mode
Optional, all modes
Optional, all modes
Optional, all modes
PS, FPP, AS
AS, AP
AS, AP
All modes
All modes
All modes
All modes
All modes
Optional
PS, FPP
AP
AP
AP
AP
AP
AP
AP
AP
AP
AP
AP
JTAG
JTAG
JTAG
JTAG
FPP
FPP
AS
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
9–67