EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 228
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–68
Table 9–21. Cyclone III Device Family Configuration Pin Summary (Part 2 of 2)
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 1 of 4)
Cyclone III Device Handbook, Volume 1
Notes to
(1) In Cyclone III devices, the CRC_ERROR pin is a dedicated output by default. Optionally, you can enable the CRC_ERROR pin as an open-drain
(2) AP configuration is for Cyclone III devices only.
MSEL [3..0]
nCONFIG
nSTATUS
Bank
5
5
Pin Name
output in the CRC Error Detection tab from the Device and Pin Options dialog box.
Table
DEV_OE
DEV_CLRn
9–21:
Description
Mode
User
N/A
N/A
N/A
Table 9–22
your board for successful configuration. Some of these pins may not be required for
your configuration scheme.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration
Scheme
lists the dedicated configuration pins that must be connected properly on
All
All
All
Input/Output
Input
Input
Bidirectional
open-drain
Pin Type
Input
Input
Dedicated
—
—
4-bit configuration input that sets the Cyclone III device
family configuration scheme. These pins must be hardwired
to V
pull-down resistors that are always active.
Some of the smaller devices or package options of
Cyclone III devices do not have the MSEL[3] pin; therefore,
the AP configuration scheme is not supported.
Configuration control input. Pulling this pin low with external
circuitry during user mode causes the Cyclone III device
family to lose its configuration data, enter a reset state, and
tri-state all I/O pins. Returning this pin to a logic-high level
starts a reconfiguration.
The Cyclone III device family drives nSTATUS low
immediately after power-up and releases it after the POR
time.
■
■
Driving nSTATUS low after configuration and initialization
does not affect the configured device. If you use a
configuration device, driving nSTATUS low causes the
configuration device to attempt to configure the device, but
because the device ignores transitions on nSTATUS in user
mode, the device does not reconfigure. To start a
reconfiguration, nCONFIG must be pulled low.
Status output. If an error occurs during configuration,
nSTATUS is pulled low by the target device.
Status input. If an external source (for example, another
Cyclone III device family) drives the nSTATUS pin low
during configuration or initialization, the target device
enters an error state.
C CA
or GND. The MSEL[3..0] pins have internal 9-kΩ
Powered By
V
V
CC IO
CC IO
Description
© December 2009 Altera Corporation
Configuration Mode
Optional, AP
Optional, AP
Configuration Features
(2)
(2)