EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 59
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Architecture
Table 4–2. Number of Multipliers in the Cyclone III Device Family (Part 2 of 2)
Architecture
© December 2009
Notes to
(1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit
(2) The total number of multipliers may vary, depending on the multiplier mode you use.
Device Family
Cyclone III LS
coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.
Table
f
f
4–2:
Altera Corporation
For more information about M9K memory blocks of the Cyclone III device family,
refer to the
For more information about soft multipliers, refer to
in FPGA Devices.
Each embedded multiplier consists of the following elements:
■
■
■
Figure 4–2
Figure 4–2. Multiplier Block Architecture
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
Multiplier stage
Input and output registers
Input and output interfaces
Device
shows the multiplier block architecture.
Memory Blocks in Cyclone III Devices
Data A
Data B
Embedded Multipliers
D
ENA
D
ENA
CLRN
CLRN
200
276
320
396
signa
signb
clock
Q
Q
ena
aclr
Register
Input
Embedded Multiplier Block
Soft Multipliers
(16
chapter.
D
ENA
× 16)
CLRN
333
483
666
891
Register
Output
AN 306: Implementing Multipliers
Q
(1)
Cyclone III Device Handbook, Volume 1
Total Multipliers
Data Out
1287
533
759
986
(2)
4–3