EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 12
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 12
Phase-Locked Loop
f
f
f
f
For more information about making remote system upgrade, refer to the
System Upgrade with Cyclone III Devices
Handbook.
For more information about the altremote_update megafunction, refer to the
altremote_update Megafunction User Guide.
Cyclone III PLLs have a number of advanced features available including clock
multiplication and division, phase shifting, programmable duty cycles, clock
switchover, PLL cascading, PLL dynamic reconfiguration, dynamic phase shifting,
spread-spectrum clocking, external clock outputs and control signals.
For more information about the PLL features, refer to the
Cyclone III Devices
Previously, PLLs in the Cyclone series devices’ FPGAs were designed to be configured
for a specific input frequency. The newly added voltage-controlled oscillator (VCO)
range detector in the Cyclone III PLLs, together with the dynamic phase
reconfiguration and PLL reconfiguration, enable the support for advanced display
applications where the PLL input frequency may not be known ahead of time or may
change.
For information about the VCO range detector and the reference design to support the
unknown F
with PLLs
PLL Applications
In general, you can use the PLLs for frequency synthesis and clock management. The
PLL usage helps to compensate the clock delay for large clock networks to improve
performance. You can also use the PLLs to recover clocks and clean jitter caused by
the transmission signal line. The programmability of the FPGA makes it easy to
change the parameters such as the frequency, bandwidth and duty cycle.
Before you start your design using a PLL, make sure you define the correct
applications for the PLL.
Define PLL Settings
Based on the features that are available in the Cyclone III device that you are
targeting, define the settings of the PLL based on the system requirement. The
following guidelines help you to decide on the settings.
PLL Input and Output Frequencies
Based on your system requirement, define the input frequencies and output
frequencies for the PLL. Cyclone III PLLs can operate in a particular bandwidth. If the
input frequencies and output frequencies do not meet that bandwidth, you can
cascade the PLLs. Cyclone III PLL clock inputs can only be fed by dedicated clock
input pins or outputs from another PLL. PLL clock inputs cannot be fed by internally
generated logic or clock source that originates from the general purpose I/O pins.
PLL clock outputs can drive the dedicated clock output pin or global clock networks.
white paper.
ref
video applications, refer to
chapter in volume 1 of the Cyclone III Device Handbook.
chapter in volume 1 of the Cyclone III Device
Supporting Unknown F
Clock Networks and PLLs in
© November 2008 Altera Corporation
REF
Video Applications
Early System Planning
Remote