EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 32
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 32
f
Clocks
Clocks are important as they have a large effect on your design’s timing accuracy,
performance, and reliability. Problems associated with the clocks can cause functional
and timing problems in the design. Pay attention to the following sub-sections that are
related to clocks when you are in the designing stage.
Global Clock Pins and Clock Networks
Use dedicated clock pins and global clock routing for clock signal input to your
design. The dedicated clock pins drive the clock network directly, ensuring lower
skew compared to using normal I/O pins. High clock skew might cause hold time
violation. The clock network drives the entire Cyclone III device and you can use the
global clock to drive all the features in the device, for example the M9K memory and
logic array blocks. Using the clock network ensures you have a predictable and more
constant delay for signals that have high fan-out. You can also use the clock pins and
clock network to drive control signals such as asynchronous reset.
For more information about the global clock pins and clock networks, refer to the
Clock Networks and PLLs in Cyclone III Devices
Device Handbook.
Internally Generated Clocks
Combinational logic output is not immune to glitches as it depends on the inputs to
the circuit. The input signals may arrive at the combinational logic circuit at different
times and cause glitches. Moreover, the input signals may have glitches and the
combinational logic circuitry does not filter out these glitches. If you use this
combinational logic output signal as a clock to other circuitries, these glitches can
cause functional problems.
Always register the input signals to the combinational circuitry and the output signal
from that circuitry that is used as a clock
higher frequency than the clock generated internally. Registering the input signals to
the combinational circuitry ensures the arrival of the signals to the circuit is controlled
by the clock, and any glitches are filtered in the input signals. By registering the
output signals from the circuit, you can filter out any glitches generated by the
circuitry.
Figure 5. Registering the Input and Output Signals
Clock Signal of
Higher Frequency
Clock Signal of
Higher Frequency
Input
Signal
Input
Signal
Clock Generation
(Figure
Combinational
Circuitry
chapter in volume 1 of the Cyclone III
5) if you have a clock signal with a
© November 2008 Altera Corporation
Generated
Clock Signal
Design and Compilation