EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 36
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 36
Design and Compilation
f
For more information about using the incremental compilation flows in the Quartus II
software, as well as important guidelines for creating design partitions and a design
floorplan, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based
Design
chapter in volume 1 of the Quartus II Handbook.
Design Partitions
When partitioning a design for an FPGA, register the partition of the I/O boundaries
to keep critical timing paths inside one partition that can be optimized independently.
When the design partitions are specified, you can use the Incremental Compilation
Advisor to ensure that the partitions meet Altera's recommendations.
Having the source code for each design block in a separate file allows you to make
changes to the block separately. If you use a third-party synthesis tool, create a
separate .vqm or .edf netlist for each design partition in your synthesis tool. Refer to
your synthesis tool documentation for information on the support for the Quartus II
incremental compilation. Use the hierarchy in your design to provide more flexibility
when partitioning. The top level of the hierarchy should have very little logic, and the
lower-level design blocks contain the most logic.
Timing Budget and Resource Allocation
In a team-based design, if you optimize the lower-level partitions separately, any
unregistered path that crosses between the partitions are not optimized as an entire
path when the partitions are integrated. For each unregistered timing path that
crosses between the partitions, make the timing assignments on the corresponding
I/O path in each partition to constrain both ends of the path to the budgeted timing
delay. The software optimizes the paths appropriately so the paths can meet the
top-level design requirements when the partitions are connected together in the
top-level design.
When performing incremental compilation, the software synthesizes each partition
separately with no data about the resources used in other partitions. Allocating
resource utilization among the design partitions for example logic, memory,
multipliers, PLLs and global routing signals avoids any problems with conflicting
resources when all the partitions are integrated.
Planning in Bottom-Up and Team-Based Flows
In bottom-up design flows, top-level project information, such as the pin locations,
physical constraints, and timing requirements, should be communicated to the
designers of the lower-level partitions before they start their design to avoid problems
during system integration.
The system architect can plan the design partitions at the top level and use the
Quartus II incremental compilation to communicate information to lower-level
designers through automatically-generated scripts. The Quartus II software’s
Generate bottom-up design partition scripts option automates the process of
transferring top-level project information to lower-level modules. The software
provides a project manager interface for managing project information in the top-level
design.
© November 2008 Altera Corporation