EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 58
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 58
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Quick Design Debugging Using SignalProbe chapter in volume 3 of the Quartus II
Handbook
Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume
3 of the Quartus II Handbook
In-System Debugging Using External Logic Analyzers chapter in volume 3 of the
Quartus II Handbook
In-System Updating of Memory and Constants chapter in volume 3 of the Quartus II
Handbook
Design Debugging Using In-System Sources and Probes chapter in volume 3 of the
Quartus II Handbook
sld_virtual_jtag Megafunction User Guide
AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O
Systems
I/O Management chapter in volume 2 of the Quartus II Handbook
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines
AN 224: High-Speed Board Layout Guidelines
AN 315: Guidelines for Designing High-Speed FPGA PCBs
Signal Integrity Analysis with Third-Party Tools chapter in volume 3 of the Quartus II
Handbook
Cyclone III Device Family Pin Connection Guidelines
Hot Socketing and Power-On Reset in Cyclone III Devices chapter in volume 1 of the
Cyclone III Device Handbook
JTAG Configuration and ISP Troubleshooter
FPGA Configuration Troubleshooter
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook
Synthesis in volume 1 of the Quartus II Handbook
Volume 4: SOPC Builder of the Quartus II Handbook
Design Recommendations for Altera Devices and the Quartus II Design Assistant
chapter in volume 1 of the Quartus II Handbook
altclkctrl Megafunction User Guide
altpll Megafunction User Guide
Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1
of the Quartus II Handbook
Analyzing and Optimizing the Design Floorplan chapter in volume 2 of the Quartus II
Handbook
Power Optimization chapter in volume 2 of the Quartus II Handbook
Design Space Explorer chapter in volume 2 of the Quartus II Handbook
Quartus II Classic Timing Analyzer chapter of the Quartus II Handbook
Software Settings section in volume 2 of the Configuration Handbook
© November 2008 Altera Corporation
Referenced Documents