EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 65
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Clock Networks
GCLK Network
© December 2009
CIII51006-3.2
f
Altera Corporation
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone
LS devices).
This chapter includes the following sections:
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The Cyclone III device family provides up to 16 dedicated clock pins (CLK[15..0])
that can drive the global clocks (GCLKs). The Cyclone III device family supports four
dedicated clock pins on each side of the device except EP3C5 and EP3C10 devices.
EP3C5 and EP3C10 devices only support four dedicated clock pins on the left and
right sides of the device.
For more information about the number of GCLK networks in each device density,
refer to the
GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
“Clock Networks” on page 5–1
“PLLs in the Cyclone III Device Family” on page 5–9
“Cyclone III Device Family PLL Hardware Overview” on page 5–10
“Clock Feedback Modes” on page 5–12
“Hardware Features” on page 5–15
“Programmable Bandwidth” on page 5–22
“Phase Shift Implementation” on page 5–22
“PLL Cascading” on page 5–24
“PLL Reconfiguration” on page 5–24
“Spread-Spectrum Clocking” on page 5–32
“PLL Specifications” on page 5–32
Cyclone III Device Family Overview
5. Clock Networks and PLLs in the
®
III device family (Cyclone III and Cyclone III
chapter.
Cyclone III Device Family
Cyclone III Device Handbook, Volume 1