EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 46

IC APEX 20KE FPGA 100K 324-FBGA

EP20K100EFC324-2

Manufacturer Part Number
EP20K100EFC324-2
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K100EFC324-2

Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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APEX 20K Programmable Logic Device Family Data Sheet
MultiVolt I/O
Interface
46
Under hot socketing conditions, APEX 20KE devices will not sustain any
damage, but the I/O pins will drive out.
The APEX device architecture supports the MultiVolt I/O interface
feature, which allows APEX devices in all packages to interface with
systems of different supply voltages. The devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The APEX 20K VCCINT pins must always be connected to a 2.5 V power
supply. With a 2.5-V V
tolerant. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power
supply, depending on the output requirements. When VCCIO pins are
connected to a 2.5-V power supply, the output levels are compatible with
2.5-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V
systems.
Table 12
Notes to
(1)
(2)
Open-drain output pins on 5.0-V tolerant APEX 20K devices (with a pull-
up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that
require a V
to 5.0 V by the resistor. The open-drain pin will only drive low or tri-state;
it will never drive high. The rise time is dependent on the value of the pull-
up resistor and load impedance. The I
considered when selecting a pull-up resistor.
V
Table 12. 5.0-V Tolerant APEX 20K MultiVolt I/O Support
CCIO
2.5
3.3
The PCI clamping diode must be disabled to drive an input with voltages higher
than V
When V
tolerant inputs.
(V)
Table
summarizes 5.0-V tolerant APEX 20K MultiVolt I/O support.
CCIO
IH
CCIO
of 3.5 V. When the pin is inactive, the trace will be pulled up
12:
.
2.5
v
v
= 3.3 V, an APEX 20K device can drive a 2.5-V device with 3.3-V
Input Signals (V)
CCINT
v(1)
v
3.3
level, input pins are 2.5-V, 3.3-V, and 5.0-V
v(1)
v(1)
5.0
OL
current specification should be
v
v(2)
2.5
Output Signals (V)
Altera Corporation
3.3
v
5.0
v

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