EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 55

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Note to
(1)
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
ICR Instructions
SignalTap Instructions
(1)
Table 19. APEX 20K JTAG Instructions
JTAG Instruction
The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions.
Table
(1)
19:
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins. Also used by the SignalTap embedded logic analyzer.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through selected devices to adjacent devices during
normal device operation.
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO.
Used when configuring an APEX 20K device via the JTAG port with a MasterBlaster
or ByteBlasterMV
via an embedded processor.
Monitors internal device operation with the SignalTap embedded logic analyzer.
All APEX 20K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX 20K devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc). Finally, APEX 20K devices use the JTAG port to
monitor the logic operation of the device with the SignalTap embedded
logic analyzer. APEX 20K devices support the JTAG instructions shown in
Table
SignalTap instructions, they do not support boundary-scan testing or the
use of the JTAG port for configuration.
19. Although EP20K1500E devices support the JTAG BYPASS and
TM
download cable, or when using a Jam File or Jam Byte-Code File
APEX 20K Programmable Logic Device Family Data Sheet
Description
TM
55