EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 68

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APEX 20K Programmable Logic Device Family Data Sheet
68
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum driver strength.
Figure 36
Figure 36. APEX 20K f
Figure 37
parameters can be used to estimate f
Quartus II software timing analysis should be used for more accurate
timing information.
shows the f
shows the f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ESBRC
ESBWC
ESBDATASU
ESBADDRSU
ESBDD
PD
PTERMCO
ESBWESU
ESBDATACO1
ESBDATACO2
PTERMSU
SU
H
CO
LUT
LE
MAX
ESB
MAX
MAX
Timing Model
timing model for APEX 20K devices.
timing model for APEX 20KE devices. These
MAX
for multiple levels of logic.
Routing Delay
t
t
t
F20+
F1—4
F5—20
Altera Corporation