EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 96
EP4CE55F23I7
Manufacturer Part Number
EP4CE55F23I7
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I7
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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5–34
Figure 5–21. Delay Insertion Using VCO Phase Output and Counter Delay Time
PLL Cascading
Cyclone IV Device Handbook, Volume 1
CLK0
CLK1
CLK2
135
180
225
270
315
45
90
0
1/8 t
1
VCO
You can use the coarse and fine phase shifts to implement clock delays in
Cyclone IV devices.
Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The
phase shift is configurable for any number of times. Each phase shift takes about one
scanclk cycle, allowing you to implement large phase shifts quickly.
Cyclone IV devices allow cascading between general purpose PLLs and multipurpose
PLLs in normal or direct mode through the GCLK network. If your design cascades
PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the
destination (downstream) PLL must have a high-bandwidth setting.
PLL_6 and PLL7 have upstream cascading capability only.
t
d0-1
t
d0-2
t
VCO
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
PLL Cascading
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