EP3C55F484I7 Altera, EP3C55F484I7 Datasheet

IC CYCLONE III FPGA 55K 484 FBGA

EP3C55F484I7

Manufacturer Part Number
EP3C55F484I7
Description
IC CYCLONE III FPGA 55K 484 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484I7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Electrical Characteristics
Operating Conditions
© January 2010 Altera Corporation
CIII52001-3.3
1
1
This chapter describes the electric characteristics, switching characteristics, and I/O
timing for Cyclone
The following sections provide information about the absolute maximum ratings,
recommended operating conditions, DC characteristics, and other specifications for
Cyclone III devices.
When Cyclone III devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of Cyclone III devices, system designers must consider the operating
requirements in this document. Cyclone III devices are offered in commercial,
industrial, and automotive grades. Commercial devices are offered in –6 (fastest), –7,
and –8 speed grades. Industrial and automotive devices are offered only in –7 speed
grade.
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix, industrial with “I” prefix, and
automotive with “A” prefix. Commercial devices are therefore indicated as C6, C7,
and C8 per respective speed grades. Industrial and automotive devices are indicated
as I7 and A7, respectively.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone III
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions.
maximum ratings for Cyclone III devices.
Conditions beyond those listed in
Additionally, device operation at the absolute maximum ratings for extended periods
of time has adverse effects on the device.
Table 1–1. Cyclone III Devices Absolute Maximum Ratings
V
V
V
V
V
Symbol
C CINT
C CIO
C CA
C CD_P LL
I
Supply voltage for internal logic
Supply voltage for output buffers
Supply voltage (analog) for phase-locked loop
(PLL) regulator
Supply voltage (digital) for PLL
DC input voltage
®
III devices. A glossary is also included for your reference.
Parameter
1. Cyclone III Device Data Sheet
Table 1–1
cause permanent damage to the device.
(Note 1)
–0.5
–0.5
–0.5
–0.5
–0.5
Min
Cyclone III Device Handbook, Volume 2
Table 1–1
(Part 1 of 2)
lists the absolute
Max
3.75
3.95
1.8
3.9
1.8
Unit
V
V
V
V
V

EP3C55F484I7 Summary of contents

Page 1

... C CA (PLL) regulator V Supply voltage (digital) for PLL C CD_P input voltage I © January 2010 Altera Corporation 1. Cyclone III Device Data Sheet ® III devices. A glossary is also included for your reference. Table 1–1 cause permanent damage to the device. Parameter Table 1–1 lists the absolute ...

Page 2

... Table 1–2 lists the maximum allowed input overshoot voltage and Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics (Note 1) (Part Min Max Unit – — ±2000 V — ±500 V –65 150 °C –40 125 °C Table 1–2 and © January 2010 Altera Corporation ...

Page 3

... Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device idle state, lifetimes are increased. © January 2010 Altera Corporation Condition Overshoot Duration High Time ...

Page 4

... Electrical Characteristics Typ Max Unit 1.2 1.25 V 3.3 3.465 V 3 3.15 V 2.5 2.625 V 1.8 1.89 V 1.5 1.575 V 1.2 1.26 V 2.5 2.625 V 1.2 1.25 V — 3 — © January 2010 Altera Corporation ...

Page 5

... Table 1–4. Cyclone III Devices I/O Pin Leakage Current Symbol Parameter I Input pin leakage current I Tristated I/O pin leakage I OZ current © January 2010 Altera Corporation (Note 1) Conditions For commercial use For industrial use For extended temperature (5) For automotive use Standard power-on reset (POR) ...

Page 6

... I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on. (3) Maximum values depend on the actual T J (www.altera.com/support/devices/estimator/cy3-estimator/cy3-power_estimator.html) or the Quartus II PowerPlay power analyzer feature. For more information about power consumption, refer to Cyclone III Device Handbook, Volume 2 ...

Page 7

... OCT without calibration across process, temperature, and voltage. Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications Description Series OCT without calibration OCT calibration is automatically performed at device power-up for OCT enabled I/Os. © January 2010 Altera Corporation (Note 1.5 1.8 Max ...

Page 8

... V T Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics Unit Industrial and Automotive Max ±10 % ±10 % ±10 % ±10 % ±10 % Equation 1–1 to determine the final dR/dV (%/mV) –0.026 –0.039 –0.086 –0.136 –0.288 © January 2010 Altera Corporation ...

Page 9

... When VREF pin is used as regular input or output, a reduced performance of toggle rate and t higher pin capacitance. (2) C for EP3C25 is 30 pF. VREFTB © January 2010 Altera Corporation shows you the example to calculate the change of 50 Ω I/O impedance Parameter or user I/O pin REF ...

Page 10

... V Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics (Note 1) Min Typ Max Unit kΩ kΩ kΩ 108 kΩ 163 kΩ 19 143 351 kΩ kΩ kΩ kΩ kΩ 112 kΩ . CCIO Maximum 300 μ (1) CCIO © January 2010 Altera Corporation ...

Page 11

... For voltage referenced receiver input waveform and explanation of terms used in in “Glossary” on page 1–27. (2) AC load pF. (3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O © January 2010 Altera Corporation Conditions Minimum V = 3.3 V 200 ...

Page 12

... C CIO — 0.4 0.4 + 0.25 × 0.75 × 0.24 C CIO CIO + 0.25 × 0.75 × 0.24 C CIO CIO © January 2010 Altera Corporation Max + 0.04 + 0.04 0.95 0.79 — (mA) (mA) 8.1 –8.1 16.4 –16.4 6.7 –6.7 13.4 –13.4 8 –8 16 –16 8 – ...

Page 13

... I/Os) LVDS (Column 2.375 2.5 2.625 100 I/Os) BLVDS (Row I/Os) 2.375 2.5 2.625 100 (5) BLVDS (Column 2.375 2.5 2.625 100 I/Os) (5) © January 2010 Altera Corporation V (V) V (V) Swing Max Min Typ Max CIO – 0.2 — 0 – ...

Page 14

... Early Power Estimator © January 2010 Altera Corporation (3) Max 1.4 1.4 1.5 1.5 1.4 1.4 ...

Page 15

... INDUTY Input clock cycle-to-cycle jitter ≥ 100 MHz F t (4) REF INJITTER_C CJ F < 100 MHz REF f (external clock output) OUT_EXT PLL output frequency (2) © January 2010 Altera Corporation Performance C6 C7 500 437.5 500 437.5 500 437.5 500 437.5 500 437.5 500 437.5 500 437 ...

Page 16

... SCANCLK — 3.5 (6) — cycles — — 100 MHz post-scale C O specification © January 2010 Altera Corporation ...

Page 17

... EP3C40 and smaller density members support 133 MHz. Table 1–24 lists the active configuration mode specifications for Cyclone III devices. Table 1–24. Cyclone III Devices Active Configuration Mode Specifications Programming Mode Active Parallel (AP) Active Serial (AS) © January 2010 Altera Corporation Resources Used Number of Multipliers C6 1 340 1 ...

Page 18

... C8, A7 Unit Max Min Typ Max 10 — 155.5 MHz 10 — 155.5 MHz 10 — 155.5 MHz 10 — 155.5 MHz 10 — 155.5 MHz 311 10 — 311 MHz © January 2010 Altera Corporation ...

Page 19

... Device ×7 70 operation in ×4 40 Mbps ×2 20 × — 45 DUTY TCCS — — Output jitter (peak to — — peak) © January 2010 Altera Corporation (Note C6 C7, I7 Min Typ Max Min Typ 100 — 360 100 80 — 360 80 70 — 360 70 40 — ...

Page 20

... MHz 100 — 311 Mbps 80 — 311 Mbps 70 — 311 Mbps 40 — 311 Mbps 20 — 311 Mbps 10 — 311 Mbps 45 — — — 200 ps — — 550 ps — 500 — ps — 500 — ps — — © January 2010 Altera Corporation ...

Page 21

... PLL to lock from the end of device configuration. LOC K Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications of 2) Symbol f (input clock HSC LK frequency) HSIODR t DUTY © January 2010 Altera Corporation C6 C7, I7 Modes Min Max Min ×10 10 420 10 ×8 ...

Page 22

... MHz 370 10 320 MHz 402.5 10 402.5 MHz 740 100 640 Mbps 740 80 640 Mbps 740 70 640 Mbps 740 40 640 Mbps 740 20 640 Mbps 402.5 10 402.5 Mbps 400 — 400 ps 500 — 550 ps 1 — © January 2010 Altera Corporation ...

Page 23

... QDRII SRAM 1090 Note to Table 1–32: (1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row I/Os. © January 2010 Altera Corporation Interfaces. Row I/Os Hold Setup Hold C6 550 ...

Page 24

... January 2010 Altera Corporation ...

Page 25

... Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device Power-Up (Note 1) Symbol t OCTC AL Notes to Table 1–36: (1) OCT calibration takes place after device configuration, before entering user mode. © January 2010 Altera Corporation Column I/Os (ps) Row I/Os (ps) Lead Lag Lead 1092 515 1092 1250 ...

Page 26

... Max Offset Slow Corner 2.335 2.406 2.381 2.505 2.402 2.558 2.447 2.557 1.072 1.167 1.074 1.101 1.388 1.542 1.403 1.45 © January 2010 Altera Corporation Unit Unit ...

Page 27

... Input pin to Global Clock network through PLL. H HSIODR HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI). Input Waveforms for the SSTL I V SWING Differential I/O Standard © January 2010 Altera Corporation Cyclone III Devices Definitions — — — — — ...

Page 28

... JSZX JSCO — — — — — Switchover INPFD N PFD M Reconfigurable in User Mode — Chapter 1: Cyclone III Device Data Sheet Glossary t JPH t JPXZ t JSXZ CLKOUT Pins f OUT _EXT VCO VCO GCLK OUT Counters C0..C4 Phase tap © January 2010 Altera Corporation ...

Page 29

... DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. SW (Sampling HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it Window) correctly. The setup and hold times determine the ideal strobe position in the sampling window. © January 2010 Altera Corporation Definitions ...

Page 30

... RISE t Input register setup time — Cyclone III Device Handbook, Volume 2 Definitions variation and clock skew. The clock is included in the TCCS measurement — Chapter 1: Cyclone III Device Data Sheet Glossary /w). C Positive Channel ( Negative Channel ( Ground © January 2010 Altera Corporation ...

Page 31

... Differential I/O Standard, refer to Input Waveforms. V Termination voltage for SSTL, HSTL I/O Standards differential Input cross point Voltage: The voltage at which the differential input signals must AC) cross. W — X — Y — Z — © January 2010 Altera Corporation Definitions = ( REF (AC ) should not exceed REF REF (DC) — — — ...

Page 32

... Table 1–62, Table 1–63, Table 1–68, Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87, Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and Table 1–99. Chapter 1: Cyclone III Device Data Sheet Document Revision History reference. © January 2010 Altera Corporation ...

Page 33

... October 2007 1.4 July 2007 1.3 June 2007 1.2 © January 2010 Altera Corporation (Part Changes Made Updated “Operating Conditions” section and included information on ■ automotive device. Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive ■ ...

Page 34

... Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1- ■ 110 through 1-111. Added a waveform (Receiver Input Waveform) in glossary under letter “R” ■ (Table 1-112). Initial release. Chapter 1: Cyclone III Device Data Sheet Document Revision History , and I information. C CIO0 © January 2010 Altera Corporation ...

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