EP3C55F484I7 Altera, EP3C55F484I7 Datasheet

IC CYCLONE III FPGA 55K 484 FBGA

EP3C55F484I7

Manufacturer Part Number
EP3C55F484I7
Description
IC CYCLONE III FPGA 55K 484 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484I7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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®
Cyclone III Device Handbook, Volume 2
101 Innovation Drive
San Jose, CA 95134
www.altera.com
CIII5V2-3.3

EP3C55F484I7 Summary of contents

Page 1

... Innovation Drive San Jose, CA 95134 www.altera.com CIII5V2-3.3 Cyclone III Device Handbook, Volume 2 ® ...

Page 2

... Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera as- sumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

Page 3

... About–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1 Chapter 1. Cyclone III Device Data Sheet Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1– ...

Page 4

... OCT Calibration Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24 IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31 Cyclone III Device Handbook, Volume 2 © January 2010 Altera Corporation ...

Page 5

... Chapter 1 Cyclone III Device Data Sheet Revised: Part Number: CIII52001-3.3 Chapter 2 Cyclone III LS Device Data Sheet Revised: Part Number: CIII52002-1.2 © January 2010 Altera Corporation January 2010 December 2009 Chapter Revision Dates Cyclone III Device Handbook, Volume 2 ...

Page 6

... Cyclone III Device Handbook, Volume 2 Chapter Revision Dates © January 2010 Altera Corporation ...

Page 7

... Product literature Altera literature services Non-technical support (General) (Software Licensing) Note to table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions This document uses the typographic conventions shown below. Visual Cue Bold Type with Initial Capital Letters ...

Page 8

... The warning indicates information that should be read prior to starting or continuing the procedure or processes. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Chapter : Typographic Conventions . ), as well as logic © January 2010 Altera Corporation ...

Page 9

... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © January 2010 Altera Corporation Section 1. Cyclone III Device Cyclone III Device Handbook, Volume 2 ...

Page 10

...

Page 11

... C CA (PLL) regulator V Supply voltage (digital) for PLL C CD_P input voltage I © January 2010 Altera Corporation 1. Cyclone III Device Data Sheet ® III devices. A glossary is also included for your reference. Table 1–1 cause permanent damage to the device. Parameter Table 1–1 lists the absolute ...

Page 12

... Table 1–2 lists the maximum allowed input overshoot voltage and Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics (Note 1) (Part Min Max Unit – — ±2000 V — ±500 V –65 150 °C –40 125 °C Table 1–2 and © January 2010 Altera Corporation ...

Page 13

... Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device idle state, lifetimes are increased. © January 2010 Altera Corporation Condition Overshoot Duration High Time ...

Page 14

... Electrical Characteristics Typ Max Unit 1.2 1.25 V 3.3 3.465 V 3 3.15 V 2.5 2.625 V 1.8 1.89 V 1.5 1.575 V 1.2 1.26 V 2.5 2.625 V 1.2 1.25 V — 3 — © January 2010 Altera Corporation ...

Page 15

... Table 1–4. Cyclone III Devices I/O Pin Leakage Current Symbol Parameter I Input pin leakage current I Tristated I/O pin leakage I OZ current © January 2010 Altera Corporation (Note 1) Conditions For commercial use For industrial use For extended temperature (5) For automotive use Standard power-on reset (POR) ...

Page 16

... I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on. (3) Maximum values depend on the actual T J (www.altera.com/support/devices/estimator/cy3-estimator/cy3-power_estimator.html) or the Quartus II PowerPlay power analyzer feature. For more information about power consumption, refer to Cyclone III Device Handbook, Volume 2 ...

Page 17

... OCT without calibration across process, temperature, and voltage. Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications Description Series OCT without calibration OCT calibration is automatically performed at device power-up for OCT enabled I/Os. © January 2010 Altera Corporation (Note 1.5 1.8 Max ...

Page 18

... V T Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics Unit Industrial and Automotive Max ±10 % ±10 % ±10 % ±10 % ±10 % Equation 1–1 to determine the final dR/dV (%/mV) –0.026 –0.039 –0.086 –0.136 –0.288 © January 2010 Altera Corporation ...

Page 19

... When VREF pin is used as regular input or output, a reduced performance of toggle rate and t higher pin capacitance. (2) C for EP3C25 is 30 pF. VREFTB © January 2010 Altera Corporation shows you the example to calculate the change of 50 Ω I/O impedance Parameter or user I/O pin REF ...

Page 20

... V Chapter 1: Cyclone III Device Data Sheet Electrical Characteristics (Note 1) Min Typ Max Unit kΩ kΩ kΩ 108 kΩ 163 kΩ 19 143 351 kΩ kΩ kΩ kΩ kΩ 112 kΩ . CCIO Maximum 300 μ (1) CCIO © January 2010 Altera Corporation ...

Page 21

... For voltage referenced receiver input waveform and explanation of terms used in in “Glossary” on page 1–27. (2) AC load pF. (3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O © January 2010 Altera Corporation Conditions Minimum V = 3.3 V 200 ...

Page 22

... C CIO — 0.4 0.4 + 0.25 × 0.75 × 0.24 C CIO CIO + 0.25 × 0.75 × 0.24 C CIO CIO © January 2010 Altera Corporation Max + 0.04 + 0.04 0.95 0.79 — (mA) (mA) 8.1 –8.1 16.4 –16.4 6.7 –6.7 13.4 –13.4 8 –8 16 –16 8 – ...

Page 23

... I/Os) LVDS (Column 2.375 2.5 2.625 100 I/Os) BLVDS (Row I/Os) 2.375 2.5 2.625 100 (5) BLVDS (Column 2.375 2.5 2.625 100 I/Os) (5) © January 2010 Altera Corporation V (V) V (V) Swing Max Min Typ Max CIO – 0.2 — 0 – ...

Page 24

... Early Power Estimator © January 2010 Altera Corporation (3) Max 1.4 1.4 1.5 1.5 1.4 1.4 ...

Page 25

... INDUTY Input clock cycle-to-cycle jitter ≥ 100 MHz F t (4) REF INJITTER_C CJ F < 100 MHz REF f (external clock output) OUT_EXT PLL output frequency (2) © January 2010 Altera Corporation Performance C6 C7 500 437.5 500 437.5 500 437.5 500 437.5 500 437.5 500 437.5 500 437 ...

Page 26

... SCANCLK — 3.5 (6) — cycles — — 100 MHz post-scale C O specification © January 2010 Altera Corporation ...

Page 27

... EP3C40 and smaller density members support 133 MHz. Table 1–24 lists the active configuration mode specifications for Cyclone III devices. Table 1–24. Cyclone III Devices Active Configuration Mode Specifications Programming Mode Active Parallel (AP) Active Serial (AS) © January 2010 Altera Corporation Resources Used Number of Multipliers C6 1 340 1 ...

Page 28

... C8, A7 Unit Max Min Typ Max 155.5 10 — 155.5 MHz 155.5 10 — 155.5 MHz 155.5 10 — 155.5 MHz 155.5 10 — 155.5 MHz 155.5 10 — 155.5 MHz 311 10 — 311 MHz © January 2010 Altera Corporation ...

Page 29

... Device ×7 70 operation in ×4 40 Mbps ×2 20 × — 45 DUTY TCCS — — Output jitter (peak to — — peak) © January 2010 Altera Corporation (Note C6 C7, I7 Min Typ Max Min Typ 100 — 360 100 80 — 360 80 70 — 360 70 40 — ...

Page 30

... MHz 100 — 311 Mbps 80 — 311 Mbps 70 — 311 Mbps 40 — 311 Mbps 20 — 311 Mbps 10 — 311 Mbps 45 — — — 200 ps — — 550 ps — 500 — ps — 500 — ps — — © January 2010 Altera Corporation ...

Page 31

... PLL to lock from the end of device configuration. LOC K Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications of 2) Symbol f (input clock HSC LK frequency) HSIODR t DUTY © January 2010 Altera Corporation C6 C7, I7 Modes Min Max Min ×10 10 420 10 ×8 ...

Page 32

... MHz 370 10 320 MHz 402.5 10 402.5 MHz 740 100 640 Mbps 740 80 640 Mbps 740 70 640 Mbps 740 40 640 Mbps 740 20 640 Mbps 402.5 10 402.5 Mbps 400 — 400 ps 500 — 550 ps 1 — © January 2010 Altera Corporation ...

Page 33

... QDRII SRAM 1090 Note to Table 1–32: (1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row I/Os. © January 2010 Altera Corporation Interfaces. Row I/Os Hold Setup Hold C6 550 ...

Page 34

... January 2010 Altera Corporation ...

Page 35

... Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device Power-Up (Note 1) Symbol t OCTC AL Notes to Table 1–36: (1) OCT calibration takes place after device configuration, before entering user mode. © January 2010 Altera Corporation Column I/Os (ps) Row I/Os (ps) Lead Lag Lead 1092 515 1092 1250 ...

Page 36

... Max Offset Slow Corner 2.335 2.406 2.381 2.505 2.402 2.558 2.447 2.557 1.072 1.167 1.074 1.101 1.388 1.542 1.403 1.45 © January 2010 Altera Corporation Unit Unit ...

Page 37

... Input pin to Global Clock network through PLL. H HSIODR HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI). Input Waveforms for the SSTL I V SWING Differential I/O Standard © January 2010 Altera Corporation Cyclone III Devices Definitions — — — — — ...

Page 38

... JSZX JSCO — — — — — Switchover INPFD N PFD M Reconfigurable in User Mode — Chapter 1: Cyclone III Device Data Sheet Glossary t JPH t JPXZ t JSXZ CLKOUT Pins f OUT _EXT VCO VCO GCLK OUT Counters C0..C4 Phase tap © January 2010 Altera Corporation ...

Page 39

... DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. SW (Sampling HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it Window) correctly. The setup and hold times determine the ideal strobe position in the sampling window. © January 2010 Altera Corporation Definitions ...

Page 40

... RISE t Input register setup time — Cyclone III Device Handbook, Volume 2 Definitions variation and clock skew. The clock is included in the TCCS measurement — Chapter 1: Cyclone III Device Data Sheet Glossary /w). C Positive Channel ( Negative Channel ( Ground © January 2010 Altera Corporation ...

Page 41

... Differential I/O Standard, refer to Input Waveforms. V Termination voltage for SSTL, HSTL I/O Standards differential Input cross point Voltage: The voltage at which the differential input signals must AC) cross. W — X — Y — Z — © January 2010 Altera Corporation Definitions = ( REF (AC ) should not exceed REF REF (DC) — — — ...

Page 42

... Table 1–62, Table 1–63, Table 1–68, Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87, Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and Table 1–99. Chapter 1: Cyclone III Device Data Sheet Document Revision History reference. © January 2010 Altera Corporation ...

Page 43

... October 2007 1.4 July 2007 1.3 June 2007 1.2 © January 2010 Altera Corporation (Part Changes Made Updated “Operating Conditions” section and included information on ■ automotive device. Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive ■ ...

Page 44

... Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1- ■ 110 through 1-111. Added a waveform (Receiver Input Waveform) in glossary under letter “R” ■ (Table 1-112). Initial release. Chapter 1: Cyclone III Device Data Sheet Document Revision History , and I information. C CIO0 © January 2010 Altera Corporation ...

Page 45

... Battery back-up power supply for design security volatile key register V DC input voltage I © December 2009 Altera Corporation 2. Cyclone III LS Device Data Sheet ® III LS devices. A glossary is also included for your reference. Table 2–1 may cause permanent damage to the Parameter Table 2–1 ...

Page 46

... Electrical Characteristics (Note 1) (Part Min Max Unit – — ±2000 V — ±500 V –65 150 °C –40 100 °C Table 2–2 and Unit 100 % 95.67 % 55.24 % 31.97 % 18.52 % 10.74 % 6.23 % 3.62 % 2.1 % 1.22 % 0.71 % 0.41 % 0.14 % 0.047 % © December 2009 Altera Corporation ...

Page 47

... Supply voltage for output buffers, 1.2-V operation V (3) Supply (analog) voltage for PLL regulator (3) Supply (digital) voltage for PLL C CD_P LL © December 2009 Altera Corporation 4.2 V 4.1 V 3.3 V ΔT T 2–3. All supplies must be strictly monotonic without plateaus. (Note 1) (2) , Conditions — ...

Page 48

... Typ Max Unit 1.2 3.0 3.3 V –0.5 — 3 — CIO 0 — 85 °C –40 — 100 °C 50 µs — — 50 µs — — — — (Note 1) , (2) Min Typ Max Unit μA –10 — 10 μA –10 — 10 © December 2009 Altera Corporation ...

Page 49

... OCT Specifications Table 2–6 lists the variation of OCT without calibration across process, temperature, and voltage (PVT). Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications Description Series OCT without calibration © December 2009 Altera Corporation (Note 1.5 1.8 Max Min ...

Page 50

... Table 2–8 and Equation 2–1 to determine the final OCT dR/dT (%/°C) 0.262 0.234 0.219 0.199 0.161 © December 2009 Altera Corporation Electrical Characteristics Unit ±10 % ±10 % ±10 % ±10 % ±10 % (Note 1) dR/dV (%/mV) –0.026 –0.039 –0.086 – ...

Page 51

... Symbol C Input capacitance on top/bottom I/O pins IOTB C Input capacitance on left/right I/O pins IOLR Input capacitance on left/right I/O pins with true LVDS C LV DSLR output © December 2009 Altera Corporation (Note 1), (2), (3), (4), (5), (6) (7) ( (|ΔR |/100 + 1) ––––– ( ΔR /100 + 1 – ...

Page 52

... When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and t due to higher pin capacitance Cyclone III Device Handbook, Volume 2 Chapter 2: Cyclone III LS Device Data Sheet Parameter or user I/O pin REF or user I/O pin REF Electrical Characteristics Typical – Typical – Unit QFP FBGA © December 2009 Altera Corporation ...

Page 53

... Symbol I IOPIN( IOPIN(A C) Note to Table 2–11: (1) The I/O ramp rate more. For ramp rates faster than 10 ns, |IIOPIN dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate. © December 2009 Altera Corporation Conditions V = 3.3 V ± 5% (2), ( 3.0 V ± 5% (2), ( 2.5 V ± ...

Page 54

... V – 0.2 2 –2 C CIO 0.45 2.4 4 –4 0.2 V – 0.2 0.1 –0.1 C CIO 0.4 2.0 1 –1 0.45 V – 0.45 2 – 0. –2 C CIO –2 C CIO 1.5 –0 CIO 0 1.5 –0 CIO Systems. © December 2009 Altera Corporation ...

Page 55

... HSTL-12 V – REF REF –0.15 Class I 0.08 0.08 HSTL-12 V – REF REF –0.15 Class II 0.08 0.08 © December 2009 Altera Corporation V (V) REF Min Typ Max 1.19 1.25 1.31 0.833 0.9 0.969 0.85 0.9 0.95 0.71 0.75 0.79 (1) 0 (1) 0. ...

Page 56

... CIO (mV) (2) V (V) ( Min Typ Max — — — — — — — — — — — — 247 — 600 1.125 1.25 1.375 247 — 600 1.125 1.25 1.35 © December 2009 Altera Corporation ...

Page 57

... The PowerPlay power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. © December 2009 Altera Corporation (Note 1) (Part (mV) V ...

Page 58

... Switching Characteristics Early Power Estimator Unit I7 437.5 MHz 437.5 MHz 437.5 MHz 437.5 MHz Min Typ Max Unit — — 450 MHz 5 — 325 MHz 600 — 1300 MHz 40 — — — 0.15 UI — — ±750 ps © December 2009 Altera Corporation ...

Page 59

... Quartus II software in the PLL summary section of the compilation report takes into consideration the V CO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f © December 2009 Altera Corporation (Note 4) (Part (Preliminary) Parameter ≥ ...

Page 60

... LEs C7 and I7 Memory 47 1 274 0 1 274 0 1 274 0 1 274 DCLK 133 100 DCLK Range © December 2009 Altera Corporation Switching Characteristics Unit C8 260 MHz 200 MHz Unit C8 238 MHz 238 MHz 238 MHz 238 MHz Unit MHz MHz Unit ...

Page 61

... HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specification Table 2–26 through devices. For more information about the definitions of high-speed timing specifications, refer to © December 2009 Altera Corporation (Note 2) Parameter (1) (1) (1) (1) (1) (1) “ ...

Page 62

... Mbps — 311 Mbps — 311 Mbps — — 200 ps — 550 ps 500 — ps 500 — ps — Unit Min Typ Max 10 — 85 MHz 10 — 85 MHz 10 — 85 MHz 10 — 85 MHz 10 — 85 MHz 10 — 170 MHz © December 2009 Altera Corporation ...

Page 63

... HSC LK frequency) ×4 ×2 ×1 ×10 ×8 ×7 Device operation in Mbps ×4 ×2 ×1 t — DUTY TCCS — © December 2009 Altera Corporation (Part (Preliminary) C7 and I7 Modes Min Typ Max ×10 100 — 170 ×8 80 — 170 ×7 70 — 170 ×4 40 — ...

Page 64

... C8 Unit Min Max 10 320 MHz 10 320 MHz 10 320 MHz 10 320 MHz 10 320 MHz 10 402.5 MHz 100 640 Mbps 80 640 Mbps 70 640 Mbps 40 640 Mbps 20 640 Mbps 10 402.5 Mbps — 200 ps — 550 ps — © December 2009 Altera Corporation ...

Page 65

... PLL to lock from the end of device configuration. LOC K Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications (Part (Preliminary) Symbol f (input clock HSC LK frequency) HSIODR SW © December 2009 Altera Corporation (Preliminary) C7 and I7 Modes Min Max ×10 10 320 ×8 10 320 × ...

Page 66

... Wraparound Mode (ps) Hold Setup Hold 715 985 930 740 970 915 855 1085 1030 870 1115 1055 855 1185 1125 1005 1210 1150 800 1040 985 825 1000 945 900 1130 1075 © December 2009 Altera Corporation ...

Page 67

... The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard. (2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global clock network. © December 2009 Altera Corporation Column I/Os (ps) Row I/Os (ps) Lead ...

Page 68

... Chapter 2: Cyclone III LS Device Data Sheet Switching Characteristics (Note 1), (2) (Preliminary) C8 Unit Min Max Maximum Unit 20 µs (Note 1), (2) Max Offset Slow Corner Unit 0.56 1.077 1.182 1.087 ns © December 2009 Altera Corporation ...

Page 69

... For more information about the Excel-based I/O timing spreadsheet, refer to the Cyclone III Devices All specifications are representative of worst-case supply voltage and junction temperature conditions. Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (t hold time (t ) ...

Page 70

... Cyclone III Device Handbook, Volume 2 Chapter 2: Cyclone III LS Device Data Sheet Definitions — — — — — JCP JPSU_TDI JPSU_TMS JCH JCL t t JPZX JPCO t t JSSU JSH JSZX JSCO — — — — — Glossary REF JPH t JPXZ JSXZ © December 2009 Altera Corporation ...

Page 71

... Single-Ended Waveform Receiver Input Waveform R Differential Input Waveform RSKM (Receiver High-speed I/O Block: The total margin left after accounting for the sampling window and input skew TCCS. RSKM = (TUI – SW – TCCS margin) © December 2009 Altera Corporation Definitions Switchover INPFD N PFD CP M Reconfigurable in User Mode — ...

Page 72

... Delay from the PLL inclk pad to the I/O output register. Cyclone III Device Handbook, Volume 2 Definitions OH V REF OL variation and clock skew. The clock is included in the TCCS measurement Chapter 2: Cyclone III LS Device Data Sheet Glossary V CCIO IH(DC) V IL(DC) V IL( /w). C © December 2009 Altera Corporation ...

Page 73

... Transmitter output waveforms for the LVDS, mini-LVDS, PPDS, and RSDS differential I/O standards Single-Ended Waveform Transmitter Output Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) t Signal low-to-high transition time (20–80%). RISE t Input register setup time — © December 2009 Altera Corporation Definitions — 2–29 Positive Channel ( Negative Channel ( Ground 0 V ...

Page 74

... AC differential Input cross point Voltage—The voltage at which the differential input signals AC) must cross. W — X — Y — Z — Cyclone III Device Handbook, Volume 2 Chapter 2: Cyclone III LS Device Data Sheet Definitions = ( must not exceed REF REF (DC) — — — — © December 2009 Altera Corporation Glossary = V – noise. The REF (AC ) REF (DC) ...

Page 75

... Table 2–40. Document Revision History Date Version December 2009 1.2 July 2009 1.1 June 2009 1.0 © December 2009 Altera Corporation Changes Made Updated Table 2–19 through Table 2–34, ■ Updated the “Periphery Performance” on page 2–17 ■ ...

Page 76

... Cyclone III Device Handbook, Volume 2 Chapter 2: Cyclone III LS Device Data Sheet Document Revision History © December 2009 Altera Corporation ...

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