EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 2

IC CYCLONE III FPGA 55K 484 FBGA

EP3C55F484I7

Manufacturer Part Number
EP3C55F484I7
Description
IC CYCLONE III FPGA 55K 484 FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C55F484I7

Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Page 2
Table 2. Affected Devices
Quartus II Software Workaround
External Memory Specification for DDR2 SDRAM
Cyclone III Device Family Errata Sheet
Cyclone III 65-nm: All devices
Cyclone III 60-nm: EP3C55, EP3C80, and EP3C120 devices
Cyclone III LS: EP3CLS150 and EP3CLS200 devices
f
This issue only affects the read operation. The M9K write operation and the M9K
memory cell array content are not affected. In addition, the issue is not a wear-out
mechanism and does not affect the long-term reliability of the devices.
The affected Cyclone III and Cyclone III LS devices can be distinguished by the die
revision identifier (Z) and the fab process code identifier (
date code marked on the top side of the device.
Table 2
Figure 1. Altera Data Code Marking Format
A Quartus II software solution is available to work around this issue. To resolve the
problem, the solution disables up to eight data bits in the widest data width mode.
Applying the software solution may require additional M9K resources. If a fitter error
occurs, contact Altera for additional support.
For more information about applying this solution, refer to the
M9K memory block read issue in Cyclone III devices using the Quartus II software
solution?” section in the
In the Quartus
grades supported full-rate DDR2 SDRAM with a maximum clock rate of up to
167 MHz and the Cyclone III C6 speed grade supported full-rate DDR2 SDRAM with
a maximum clock rate of up to 200 MHz on column I/Os.
In the Quartus II software version 9.1 and beyond, the Cyclone III all speed grades
full-rate DDR2 SDRAM maximum clock rate specifications on column I/Os have been
downgraded. The current specifications are listed in
The downgrade of the maximum clock rate is due to the Quartus II software tool’s
inability to achieve push-button placement at the faster clock rates with the DDR2
SDRAM High-Performance Controller II.
If you are using the High-Performance Controller, you are not affected by this
downgrade.
Device
lists the devices affected by the M9K memory read issue.
®
II software version 9.0, the Cyclone III C7, C8, I7, and A7 speed
Knowledge
Database.
Die Revision (Z)
All Revisions
A
A
Figure 1
External Memory Specification for DDR2 SDRAM
Table
shows the date code format.
3.
) found in the Altera
© June 2010 Altera Corporation
Fab Process Code (
“How do I resolve the
A5, A0
AA
AA
®
)