EP2S15F484C4 Altera, EP2S15F484C4 Datasheet - Page 100
![IC STRATIX II FPGA 15K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S15F484C4
Manufacturer Part Number
EP2S15F484C4
Description
IC STRATIX II FPGA 15K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F484C4
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
15600
# I/os (max)
342
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
15600
Ram Bits
419328
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1104
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S15F484C4
Manufacturer:
ALTERA30
Quantity:
146
Part Number:
EP2S15F484C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S15F484C4N
Manufacturer:
ALTERA
Quantity:
325
Part Number:
EP2S15F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
I/O Structure
2–92
Stratix II Device Handbook, Volume 1
f
f
f
Differential On-Chip Termination
Stratix II devices support internal differential termination with a nominal
resistance value of 100 Ω for LVDS or HyperTransport technology input
receiver buffers. LVPECL input signals (supported on clock pins only)
require an external termination resistor. Differential on-chip termination
is supported across the full range of supported differential data rates as
shown in the DC & Switching Characteristics chapter in volume 1 of the
Stratix II Device Handbook.
For more information on differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
For more information on tolerance specifications for differential on-chip
termination, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Series Termination Without Calibration
Stratix II devices support driver impedance matching to provide the I/O
driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Stratix II devices support on-chip series
termination for single-ended I/O standards with typical R
and 50 Ω. Once matching impedance is selected, current drive strength is
no longer selectable.
support on-chip series termination without calibration.
On-Chip Series Termination with Calibration
Stratix II devices support on-chip series termination with calibration in
column I/O pins in top and bottom banks. There is one calibration circuit
for the top I/O banks and one circuit for the bottom I/O banks. Each
on-chip series termination calibration circuit compares the total
impedance of each I/O buffer to the external 25- or 50-Ω resistors
connected to the RUP and RDN pins, and dynamically enables or disables
the transistors until they match. Calibration occurs at the end of device
configuration. Once the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
For more information on series on-chip termination supported by
Stratix II devices, refer to the Selectable I/O Standards in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
Table 2–17
shows the list of output standards that
Altera Corporation
S
values of 25
May 2007