EP2S15F484C4 Altera, EP2S15F484C4 Datasheet - Page 101
![IC STRATIX II FPGA 15K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S15F484C4
Manufacturer Part Number
EP2S15F484C4
Description
IC STRATIX II FPGA 15K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F484C4
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
15600
# I/os (max)
342
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
15600
Ram Bits
419328
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1104
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S15F484C4
Manufacturer:
ALTERA30
Quantity:
146
Part Number:
EP2S15F484C4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S15F484C4N
Manufacturer:
ALTERA
Quantity:
325
Part Number:
EP2S15F484C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
May 2007
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For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Parallel Termination with Calibration
Stratix II devices support on-chip parallel termination with calibration for
column I/O pins only. There is one calibration circuit for the top I/O
banks and one circuit for the bottom I/O banks. Each on-chip parallel
termination calibration circuit compares the total impedance of each I/O
buffer to the external 50-Ω resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. Once the calibration
circuit finds the correct impedance, it powers down and stops changing
the characteristics of the drivers.
1
For more information on on-chip termination supported by Stratix II
devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
MultiVolt I/O Interface
The Stratix II architecture supports the MultiVolt I/O interface feature
that allows Stratix II devices in all packages to interface with systems of
different supply voltages.
The Stratix II VCCINT pins must always be connected to a 1.2-V power
supply. With a 1.2-V V
tolerant. The VCCIO pins can be connected to either a 1.5-, 1.8-, 2.5-, or
3.3-V power supply, depending on the output requirements. The output
levels are compatible with systems of the same voltage as the power
supply (for example, when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems).
The Stratix II VCCPD power pins must be connected to a 3.3-V power
supply. These power pins are used to supply the pre-driver power to the
output buffers, which increases the performance of the output pins. The
VCCPD pins also power configuration input pins and JTAG input pins.
On-chip parallel termination with calibration is only supported
for input pins.
CCINT
level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-V
Stratix II Device Handbook, Volume 1
Stratix II Architecture
2–93