EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 203
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Table 7–3. Number of DQ/DQS Groups per Side in Arria II GZ Devices (Part 2 of 2)—Preliminary
Figure 7–4. Number of DQ/DQS Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 358-Pin Ultra Fineline BGA
Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Arria II GX devices in the 358-pin UBGA package do not support the × 36 QDR II+/QDR II SRAM interface.
(3) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a × 4 DQ/DQS group with any of their pin members used for
December 2010 Altera Corporation
EP2AGZ225
EP2AGZ300
EP2AGZ350
Notes to
(1) Some of the ×4 groups may use R
(2) To interface with a ×36 QDR II+/QDR II SRAM device in a Arria II GZ FPGA that does not support the ×32/×36 DQ/DQS group, refer to
(3) These ×32/×36 DQ/DQS groups have 40 pins instead of 48 pins per group. You cannot place BWSn pins within the same DQ/DQS group as the
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
“Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface” on page
write data pins because of insufficient pins available.
Device
Figure
Table
(Note
7–4:
7–3:
1),
1517-pin
FineLine BGA
1517-pin
FineLine BGA
Package
(2)
Figure 7–4
side of the Arria II GX device. These figures represent the die-top view of the
Arria II GX device.
Figure 7–4
EP2AGX65 devices in the 358-pin Ultra FineLine BGA (UBGA) package.
UP
and R
through
shows the number of DQ/DQS groups per bank in EP2AGX45 and
Top/Bottom
I/O Bank 8A
22 User I/Os
22 User I/Os
I/O Bank 3A
Left/Right
×32/×36=0
×16/×18=0
×16/×18=0
×32/×36=0
All sides
×8/×9=1
×8/×9=1
and EP2AGX65 Devices in the
Side
DN
×4=2
358-Pin Ultra FineLine BGA
×4=2
pins. You cannot use these groups if you use the Arria II GZ calibrated OCT feature.
Figure 7–10
EP2AGX45
×4
26
26
26
38 User I/Os
I/O Bank 7A
38 User I/Os
I/O Bank 4A
×16/×18=1
×32/×36=0
(1)
×16/×18=1
×32/×36=0
×8/×9=2
×8/×9=2
×4=4
×4=4
show the maximum number of DQ/DQS groups per
Number of DQ/DQS Groups
×8/×9
Arria II Device Handbook Volume 1: Device Interfaces and Integration
12
12
12
18 User I/Os
I/O Bank 6A (3)
18 User I/Os
I/O Bank 5A
×16/×18=0
×32/×36=0
×16/×18=0
×32/×36=0
×8/×9=1
×8/×9=1
×4=2
×4=2
×16/×18
7–21.
4
4
4
×32/×36
2
0
0
(3)
(2)
Figure 7–14 on
page 7–17
Figure 7–15 on
page 7–18
Refer to
7–7
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