EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 266
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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EP2AGX45DF29I5N
Manufacturer:
ALTERA
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Manufacturer:
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8–26
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
Figure 8–22
Figure 8–22. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
For LVDS receivers, the Quartus II software provides the RSKM report showing SW,
TUI, and RSKM values for non-DPA mode. You can generate the RSKM by executing
the report_RSKM command in the TimeQuest analyzer. You can find the RSKM
report in the Quartus II Compilation report under TimeQuest Timing Analyzer
section.
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver
through the TimeQuest analyzer constraints menu.
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
shows the relationship between the RSKM, TCCS, and SW.
TCCS
RSKM
RSKM
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Time Unit Interval (TUI)
Clock Placement
Falling Edge
SW
Internal
TUI
SW
Clock
December 2010 Altera Corporation
Source-Synchronous Timing Budget
RSKM
RSKM
TCCS
TCCS
2
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