EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 65
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 3: Memory Blocks in Arria II Devices
Clocking Modes
Clocking Modes
Table 3–9. Internal Memory Clock Modes for Arria II Devices
December 2010 Altera Corporation
Independent
Input and output
Read and write
Single clock
Clocking Mode
Independent Clock Mode
Input and Output Clock Mode
Read and Write Clock Mode
c
True Dual-Port Mode
Arria II memory blocks support the following clocking modes:
■
■
■
■
Violating the setup or hold time on the memory block address registers could corrupt
the memory contents. This applies to both read and write operations.
Table 3–9
Arria II memory blocks can implement independent clock mode for true dual-port
memories. In this mode, a separate clock is available for each port (clock A and
clock B). Clock A controls all registers on the port A side; clock B controls all registers
on the port B side. Each port also supports independent clock enables for both port A
and port B registers, respectively. Asynchronous clears are supported only for output
latches and output registers on both ports.
Arria II memory blocks can implement input and output clock mode for true and
simple dual-port memories. In this mode, an input clock controls all registers related
to the data input to the memory block including data, address, byte enables, read
enables, and write enables. An output clock controls the data output registers.
Asynchronous clears are available on output latches and output registers only.
Arria II memory blocks can implement read and write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both the read and write clocks. Asynchronous clears
are available on data output latches and registers only.
“Independent Clock Mode” on page 3–19
“Input and Output Clock Mode” on page 3–19
“Read and Write Clock Mode” on page 3–19
“Single Clock Mode” on page 3–20
v
v
v
—
lists the supported clocking mode/memory mode combinations.
Simple Dual-Port Mode
v
v
v
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Single-Port Mode
—
v
—
v
ROM Mode
v
v
v
—
FIFO Mode
v
v
—
—
3–19
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