EP1S25F1020C7N Altera, EP1S25F1020C7N Datasheet - Page 205
EP1S25F1020C7N
Manufacturer Part Number
EP1S25F1020C7N
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F1020C7N
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F1020C7N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
January 2006
Table 4–54
clock networks.
Notes to
(1)
(2)
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
XZPLL
ZXPLL
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2
of 2)
Table 4–54. Stratix Global Clock External I/O Timing Parameters
(2)
Symbol
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
Table
Table
shows the external I/O timing parameters when using global
Setup time for input or bidirectional pin using IOE input register with
global clock fed by
Hold time for input or bidirectional pin using IOE input register with
global clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
(1),
4–53:
4–54:
(2)
CLK
CLK
pin
pin
Parameter
Parameter
Stratix Device Handbook, Volume 1
CLK
DC & Switching Characteristics
pin
Notes
(1),
4–35
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