EP1AGX90EF1152I6 Altera, EP1AGX90EF1152I6 Datasheet - Page 227
EP1AGX90EF1152I6
Manufacturer Part Number
EP1AGX90EF1152I6
Description
IC ARRIA GX FPGA 90K 1152FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX90EF1152I6
Number Of Logic Elements/cells
90220
Number Of Labs/clbs
4511
Total Ram Bits
4477824
Number Of I /o
538
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Price
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Chapter 4: DC and Switching Characteristics
External Memory Interface Specifications
Table 4–117. Fast PLL Specifications (Part 2 of 2)
External Memory Interface Specifications
© December 2009 Altera Corporation
t
Note to
(1) This is limited by the I/O f
ARESET_RECONFIG
Table
Name
4–117:
Table 4–118
circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) ,
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
Notes to
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under
(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II
Number of DQS Delay Buffer Stages
Minimum pulse width
on the
when using PLL
reconfiguration. Reset
the PLL after
scandone
MAX
Number of DQS Delay Buffer Stages
commercial conditions is 200 ps peak-to-peak or 100 ps.
software.
.
Description
areset
Table
Frequency Mode
goes high.
through
4–119:
signal
0
1
2
1
2
3
4
1
2
3
4
Table 4–122
Min
500
list Arria GX device specifications for the dedicated
(2)
Typ
—
Commercial (ps)
Frequency Range (MHz)
110
130
160
80
100 to 175
150 to 230
200 to 310
–6 Speed Grade (ps)
Max
—
105
140
35
70
Arria GX Device Handbook, Volume 1
DQS_PSERR
Industrial (ps)
Units
(Note 1)
ns
110
130
180
210
)
4–105
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