EP1S40F1020C7N Altera, EP1S40F1020C7N Datasheet - Page 69
EP1S40F1020C7N
Manufacturer Part Number
EP1S40F1020C7N
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40F1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40F1020C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40F1020C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–30. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
July 2005
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
Optional Serial Shift Register
Inputs from Previous
DSP Block
D
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
Q
Q
Q
Q
Q
Q
Q
Q
Multiplier Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
Q
Q
Q
Q
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Optional Pipeline
Register Stage
Accumulator
Accumulator
Subtractor/
Subtractor/
Adder/
Adder/
1
2
Summation Stage
for Adding Four
Multipliers Together
Stratix Device Handbook, Volume 1
Summation
Output Selection
Multiplexer
to MultiTrack
Interconnect
Stratix Architecture
Optional Output
Register Stage
2–55
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