EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 137
EP1SGX25CF672C6
Manufacturer Part Number
EP1SGX25CF672C6
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25CF672C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX25CF672C6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX25CF672C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1SGX25CF672C6ES
Manufacturer:
ALTERA
Quantity:
5
Altera Corporation
February 2005
Figure 4–42. Regional Clocks
Fast Regional Clock Network
In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins (see
Figure
networks within each half-quadrant (see
clocks can also be used for high fanout control signals, such as
asynchronous clears, presets, clock enables, or protocol control signals
such as TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast
clock networks. All devices have eight FCLK pins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. The I/O
interconnect drives this signal.
RCLK[1..0]
RCLK[3..2]
CLK[3..0]
4–43). In EP1SGX40 devices, there are two fast regional clock
RCLK[15..14]
RCLK[5..4]
CLK[7..4]
Stratix GX Device Handbook, Volume 1
RCLK[13..12]
RCLK[7..6]
CLK[15..12]
Figure
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
Recovered Clocks, or PLLs within
that Quadrant
4–44). The FCLK[1..0]
Stratix GX Architecture
Transceiver
Clocks
RCLK[11..10]
RCLK[9..8]
4–71