EP1S30F1020C6N Altera, EP1S30F1020C6N Datasheet - Page 123
EP1S30F1020C6N
Manufacturer Part Number
EP1S30F1020C6N
Description
IC STRATIX FPGA 30K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S30F1020C6N
Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
726
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
32470
# I/os (max)
726
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
32470
Ram Bits
3317184
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–63. Control Signal Selection per IOE
Altera Corporation
July 2005
Dedicated I/O
Clock [7..0]
I/O Interconnect
[15..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_cclr
io_cce_out
io_cce_in
io_cclk
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
selection.
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
shows the IOE in bidirectional configuration.
clk_in
clk_out
io_bclk[3..0]
Figure 2–63
ce_in
ce_out
io_bce[3..0]
illustrates the control signal
aclr/preset
Stratix Device Handbook, Volume 1
sclr/preset
io_bclr[3..0]
Stratix Architecture
oe
Figure 2–64
io_boe[3..0]
2–109
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