EP1SGX25DF1020C6 Altera, EP1SGX25DF1020C6 Datasheet - Page 76
EP1SGX25DF1020C6
Manufacturer Part Number
EP1SGX25DF1020C6
Description
IC STRATIX GX FPGA 25K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25DF1020C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
607
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Logic Elements
Figure 4–7. Carry Select Chain
4–10
Stratix GX Device Handbook, Volume 1
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
B5
LAB Carry-Out
0
0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
1
1
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a
NOT-gate push-back technique. Stratix GX devices support simultaneous
preset/ asynchronous load, and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one preset signal.
In addition to the clear and preset ports, Stratix GX devices provide a
chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
Sum1
Sum2
Sum3
Sum4
Sum5
Sum6
Sum7
Sum8
Sum9
Sum10
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
Carry-Out0
LUT
LUT
LUT
LUT
Carry-Out1
Sum
Altera Corporation
February 2005
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