EP1S30F1020C6 Altera, EP1S30F1020C6 Datasheet - Page 69
EP1S30F1020C6
Manufacturer Part Number
EP1S30F1020C6
Description
IC STRATIX FPGA 30K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S30F1020C6
Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
726
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
32470
# I/os (max)
726
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
32470
Ram Bits
3317184
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1419
EP1S30SF1020C6
EP1S30SF1020C6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S30F1020C6
Manufacturer:
ALTERA
Quantity:
586
Part Number:
EP1S30F1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 69 of 276
- Download datasheet (4Mb)
Figure 2–30. DSP Block Diagram for 18 × 18-Bit Configuration
Altera Corporation
July 2005
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
Optional Serial Shift Register
Inputs from Previous
DSP Block
D
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
ENA
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
CLRN
Q
Q
Q
Q
Q
Q
Q
Q
Multiplier Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
D
ENA
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
CLRN
Q
Q
Q
Q
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Optional Pipeline
Register Stage
Accumulator
Accumulator
Subtractor/
Subtractor/
Adder/
Adder/
1
2
Summation Stage
for Adding Four
Multipliers Together
Stratix Device Handbook, Volume 1
Summation
Output Selection
Multiplexer
to MultiTrack
Interconnect
Stratix Architecture
Optional Output
Register Stage
2–55
Related parts for EP1S30F1020C6
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: