EP1S30B956C6 Altera, EP1S30B956C6 Datasheet - Page 18
EP1S30B956C6
Manufacturer Part Number
EP1S30B956C6
Description
IC STRATIX FPGA 30K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S30B956C6
Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1417
EP1S30SB956C6
EP1S30SB956C6
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Logic Array Blocks
Figure 2–2. Stratix LAB Structure
2–4
Stratix Device Handbook, Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
M4K RAM blocks, or DSP blocks from the left and right can also drive an
LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 30 other LEs through fast local and direct link interconnects.
Figure 2–3
LAB
shows the direct link connection.
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
Row Interconnects of
Variable Speed & Length
Column Interconnects of
Variable Speed & Length
Altera Corporation
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
July 2005
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