EP1S25F1020C5 Altera, EP1S25F1020C5 Datasheet - Page 107
EP1S25F1020C5
Manufacturer Part Number
EP1S25F1020C5
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F1020C5
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1857
EP1S25F1020C5
EP1S25F1020C5
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S25F1020C5N
Manufacturer:
ALTERA
Quantity:
20 000
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Figure 2–55. External Clock Outputs for PLLs 5 & 6
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
e0 Counter
e1 Counter
e2 Counter
e3 Counter
The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with IOE outputs.
Two single-ended outputs are possible per output counter⎯ either two outputs of the same frequency and phase or
one shifted 180° .
EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two
pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are
programmed to have opposite polarity.
Figure
2–55:
4
From IOE (1), (2)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
(3)
Stratix Device Handbook, Volume 1
pll_out0p (3), (4)
pll_out0n (3), (4)
pll_out1p (3), (4)
pll_out1n (3), (4)
pll_out2p (3), (4)
pll_out2n (3), (4)
pll_out3p (3), (4)
pll_out3n (3), (4)
Stratix Architecture
2–93
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